Subject: Re: $table proposal
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Jan 16 2001 - 16:56:46 PST
> From john_shields@avanticorp.com Tue Jan 16 15:03:23 2001
>
> Hi Kevin,
>
> You have a lot of valuable ideas. My feedback begins with re-iterating
> that we must first stabilize and disambiguate what is defined in 2.0, including
> correcting errors.
I was more suggesting that Antrim might want to re-propose the table modelling
using a more general purpose mechanism; that way we would have less to argue
about :-)
I'm not sure everybody doing Verilog-AMS simulators wants table modelling to
be part of the standard and hence something they are obliged to support, but
I do agree we should have a formal mechanism through which it can be supported.
> I may be mistaken about the specific position we are taking on $table, because
> of its popularity in the Antrim implementation. In terms of your proposal,
> if we are already consciously defering any work on vpi-ams, I see it equally
> reasonable for us to defer examining the compiled C model issue until we get
> the higher priority things done.
I realize we may possibly stray into "vpi-ams" territory as far as implementation
goes, I was just looking to reduce the syntactic support aspect - i.e. the
declaration of an external model and how it hooks into the simulator are two
seperate issues, I think we can do the first quite quickly and leave the second
to people implementing simulators.
As I said elsewhere, secondary tools (like place & route) don't care what model
you use for a transistor, they just need a "representation stop" mechanism so
that they can tell that it is a transistor.
> I don't want to continue politely disagreeing with your enhancement suggestions because
> they do not follow the priorities. My suggestion is that we agree that there is
> window in our development of the OVI 2.1 spec for enhancement discussion,
> and we simply collect ideas as they come for that purpose. If we do not
> think the 2.1 schedule golas we have will permit doing that, then we well
> wish to agree not to take enhancements until 2.2 or change the schedule goal
> to give us time to work the suggestions.
>
> Any comments?
Some things are enhancements, others are requirements (from my perspective as a
user), some issues are about things that are wrong in the existing LRM. This is
IMO the best forum for discussing them as the teleconferences and face-to-face
meetings are not frequent enough to discuss all the technical issues. If we
fail to fix the broken parts of Verilog-AMS now, we will be stuck with them for
a very long time.
Kev.
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