Subject: Issues on if-elseif
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Mon Jan 22 2001 - 22:38:50 PST
Reply To: schandra@asc.corp.mot.com
Organization: Motorola Australia Software Center
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Location: LRM version 1.9 (15 dec 1999): section 6.4
Consider the following Verilog-AMS module:
module curly;
genvar g;
integer i;
electrical a,b;
analog begin
if(g==3) // #1
V(a) <+ transition(...); // #2
else if(i==6) // #3
V(b) <+ slew(...); // #4
else // #5
// some other code
end
endmodule
Now, the LRM defines any if() with a genvar expression as an analog if.
g==3 is a genvar expression, so conceivably the if from #1 with else at
#3 is an analog if statement;
the if at #3 with else at #5 would then be considered as a nested if
statement.
In this scenario, statement #2 is OK but #4 is wrong.
This is fine if you consider if-else as an integral statement, which the
LRM kind of says.
However, the LRM also defines if-else-if-else as a "multi-way decision".
Under this situation, the whole statement from #1 to #5 is a *single*
statement. Because the condition at #3 is not a genvar expression, the
whole thing is procedural, not analog, and therefore both #2 and #4 are
wrong.
We have a case here of the LRM contradicting itself, and the
consequences are pretty bad for analog operator usage
Regards,
From Jason
-- Srikanth Chandrasekaran EDA Solutions and Products SBU Phone: +61-8-8203 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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