Subject: Re: [D]SPF for back-annotation?
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Feb 02 2001 - 18:19:29 PST
> From pragc@www.tdl.com Fri Feb 2 18:01:36 2001
>
> Why not use SDF? It is already supported by every Verilog simulator and the
> infr-structure of programs for handling name conflicts, etc exists.
> It is extensible. There also are some new features for Verilog 2000
> that allow annotating to procedural behavioral code so extensions to allow
> annotating to analog blocks and spice should not be too hard.
> /Steve
We need to be able to back-annotate analog circuitry, SDF is only good for
digital timing - e.g. it doesn't cover crosstalk, mutual inductance or
transmission line effects.
The easiest way to handle the stuff (IMO) is to allow the inclusion of
extra circuitry in the HDL description (e.g. the full SPF) and then reconnect
the ports of the un-annotated design into it - but you need a way of disabling
the bits of the SPF that are covered by the un-annotated design (which is
awkward if it is flat).
We also need to be able to mix SDF & SPF in a single design.
Kev.
This archive was generated by hypermail 2b28 : Fri Feb 02 2001 - 18:23:23 PST