Subject: RE: Thoughts on OOMRs
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Feb 07 2001 - 10:21:44 PST
> From imw@antrim.com Wed Feb 7 09:26:10 2001
>
> The need for a declaration of the net referenced in an OOMR
> appears to be purely an artefact of the hierarchical approach
> to discipline assignment.
>
> There doesn't seem to be an inherent need for a declaration:
>
> module top;
> A a();
> B b();
> endmodule
>
> module A;
> electrical e;
> endmodule
>
> module B;
> electrical z;
> analog V(z) <+ V(top.A.e); // no ambiguity
> endmodule
I think you are correct with that example. I was thinking of:
module top;
A a();
B b()
C c()
endmodule
module A;
initial b.z = 1;
endmodule
module B; // replacing a digital module B ?
electrical z;
analog V(z) <+ I(...);
endmodule
module C;
assign p = b.z;
endmodule
- you need a discipline in A to insert a d2a and one
in C to insert an a2d. As module B is using a base discipline
you need to do something like:
...
module A;
CMOS2V_1M b.z;
initial b.z = 1;
endmodule
...
module C;
CMOS2V_PROBE b.z;
assign p = b.z;
endmodule
An alternative method is a C-like "cast" :
...
module C;
assign p = (CMOS2V_PROBE)b.z;
endmodule
- which lets you probe the same wire in different
ways from the same module.
BTW, if anyone wants to probe from procedural verilog
testbenches we could (re)introduce quick conversion e.g.:
connect function quick_a2d(node)
electrical node;
quick_a2d = (V(node) > 1.0) ? 1 : 0;
endfunction
connect quick_a2d input CMOS2V_PROBE, output digital;
...
@(posedge clock) begin
reset = (CMOS2V_PROBE)design.reset;
end
- I think something like that was in the ealier LRMs as $a2d
and $d2a. It's advantage is that no connect module is added
(permanently) to the simulation - which reduces memory
requirements.
Kev.
Kev.
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