Subject: Re: Thoughts on OOMRs
From: Jonathan Sanders (jons@cadence.com)
Date: Thu Feb 08 2001 - 08:44:28 PST
Kevin,
Graham caught most of issues but now that I look at your example
I see a big mistake. In your example below you cannot do what you
are doing in module A. If you look in the LRM it talks about context and
ownership and a net or variable is owned by one and only one context.
Since in module B net z is set in the analog block it is analog and owned
by analog. In module A you are trying to set this same signal via an OOMR
in the digital context which is not allowed.
Now if you change module A to the following:
module A ();
myinv I1 (B.z, in);
stim I2 (in);
end
Then the output net of myinv will need a discipline so that a Connect Module
can be determined based on these disciplines. Of course, since the myinv
might not have a discipline defined this can be done in a number of ways.
1) Edit the file and define it
2) Use an OOMR discipline declaration
3) Use the compiler directive DEFAULT_DISCIPLINE
Of course option 3 is the intended use model for dealing with digital blocks
that don't have disciplines defined since we cannot expect that users will
be willing to edit thousands of Verilog blocks.
As for your connectmodules example there are several errors vs the standard
but maybe you are proposing things. As for the a2d and d2a functions this
was addressed in the last cleanup effort. Since there were over twenty issues
with these modules and they provided only a subset of the connectmodule feature
of the language the committee voted to drop these.
Jon
At 12:07 AM 2/8/01, Graham Helwig wrote:
>Hello Kevin,
>
>In Verilog-A, an analog net reference is always used structurally, never
>behvaiourally (eg. to access it value). But in Verilog a digital net
>reference is used both structurally and behaviourally. The mechanism is
>not symetrical between the domains. To have a net (also branch)
>reference directly used within a (analog or digital) expression result
>in ambiguity. Does the user mean to access the potential or flow wrt to
>ground? That is why analog probe access function was specified to remove
>this ambigutiy.
>
>Now these proposed lightwieght conversion mechanisms then must assume
>that the net/branch access is poential? This is not good!
>
>Specifically, the "b.z = 1;" statement is a digital net assignment,
>therefore the the LHS is expected to refer to digital net, if it is not
>then it is an error. Similarly, the "assign p = b.z;" statement has an
>invalid RHS expression because "b.z" syntax denotes it is as digital net
>reference (not an analog one).
>
>Regards
>Graham
>
>Kevin Cameron x3251 wrote:
> >
> > > From imw@antrim.com Wed Feb 7 09:26:10 2001
> > >
> > > The need for a declaration of the net referenced in an OOMR
> > > appears to be purely an artefact of the hierarchical approach
> > > to discipline assignment.
> > >
> > > There doesn't seem to be an inherent need for a declaration:
> > >
> > > module top;
> > > A a();
> > > B b();
> > > endmodule
> > >
> > > module A;
> > > electrical e;
> > > endmodule
> > >
> > > module B;
> > > electrical z;
> > > analog V(z) <+ V(top.A.e); // no ambiguity
> > > endmodule
> >
> > I think you are correct with that example. I was thinking of:
> >
> > module top;
> > A a();
> > B b()
> > C c()
> > endmodule
> >
> > module A;
> > initial b.z = 1;
> > endmodule
> >
> > module B; // replacing a digital module B ?
> > electrical z;
> > analog V(z) <+ I(...);
> > endmodule
> >
> > module C;
> > assign p = b.z;
> > endmodule
> >
> > - you need a discipline in A to insert a d2a and one
> > in C to insert an a2d. As module B is using a base discipline
> > you need to do something like:
> >
> > ...
> > module A;
> > CMOS2V_1M b.z;
> > initial b.z = 1;
> > endmodule
> >
> > ...
> > module C;
> > CMOS2V_PROBE b.z;
> > assign p = b.z;
> > endmodule
> >
> > An alternative method is a C-like "cast" :
> >
> > ...
> > module C;
> > assign p = (CMOS2V_PROBE)b.z;
> > endmodule
> >
> > - which lets you probe the same wire in different
> > ways from the same module.
> >
> > BTW, if anyone wants to probe from procedural verilog
> > testbenches we could (re)introduce quick conversion e.g.:
> >
> > connect function quick_a2d(node)
> > electrical node;
> > quick_a2d = (node > 1.0) ? 1
> > : 0;
> > endfunction
> >
> > connect quick_a2d input CMOS2V_PROBE, output digital;
> >
> > ...
> > @(posedge clock) begin
> > reset = (CMOS2V_PROBE)design.reset;
> > end
> >
> > - I think something like that was in the ealier LRMs as $a2d
> > and $d2a. It's advantage is that no connect module is added
> > (permanently) to the simulation - which reduces memory
> > requirements.
> >
> > Kev.
> >
> > Kev.
>
>--
>-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
>Graham Helwig email: A11558@email.mot.com
> ghelwig@asc.corp.mot.com
>Telephone:+61-8-82033532 Fax:+61-8-82033501
>Motorola Australia Software Centre,
>2 Second Avenue, Technology Park, Adelaide, SA, 5095, Australia
>-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
***********************************************************
Jonathan L. Sanders
Product Engineering Director
Mixed Signal and Physical Verification Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7265
***********************************************************
This archive was generated by hypermail 2b28 : Thu Feb 08 2001 - 08:53:45 PST