Subject: Re: Thoughts on OOMRs
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Feb 08 2001 - 12:52:23 PST
> From jons@cadence.com Thu Feb 8 01:41:39 2001
>
[See web for full text]
>
> Hopefully this helps clarify some of your questions although it probably
> will result in additional questions. I am out of the country right now but if
> you still have questions on this or a view on which of the two ports the CM
> should be placed let me know.
>
> Jon
IMO the rule for inserting A/D converters is that D2As are created
in the context of the driving process, and A2Ds in the context of the
context of the receiving process. The problem we have is that currently
we can't attribute disciplines to the ends of OOMRs to get the right
A/D converters (I couldn't see the mechanism in your postings).
We also have two possible types of OOMR access from Verilog-D, static
(through ports) and dynamic (from behavioral code), the latter type
probably requires a "light weight" A/D conversion for reading, but
writing is really awkward to define (and should probably be considered
illegal for now).
Also, in the case where we are using legacy (non-editable) Verilog-D,
we need a mechanism for back-annotating disciplines to OOMRs from
outside the refering module too. There used to be a compiler directive
for setting disciplines on untyped ports, we can reintroduce it - e.g.:
`set_discipline LOGIC3V_PROBE netlist.dblk1:netlist.b3.vp,...
- which sets the dblk1 end of the OOMR.
Kev.
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