Subject: net_resolution
From: Ian Wilson (imw@antrim.com)
Date: Thu Feb 22 2001 - 16:26:01 PST
After more discussion, we agree with the proposal to eliminate the
mystical net_resolution operator.
Here's a proposal for how to overhaul the relevant sections. I have
reworked the connect module example, removing the syntax errors and
moving the collection of driver information into the analog block so there
are no problems with unsynchronized access to shared variables as in the
original.
--ian
8.10.5
- change title from "net_resolution" to "Driver-Receiver Access in Connect Modules"
- replace body by:
When a connect module containing a digital inout port is added to a net,
the drivers and receivers of that net become decoupled. The outputs of the
drivers are combined using standard Verilog-D resolution mechanisms. This
resolved value may be accessed in the connect module by reading the inout
port. The receivers can be driven by writing to the inout port. Although
the same identifier is used for the input and output directions of the port,
the effect is the same as if there were distinct, unidirectional, ports.
No default processing is applied within a connect module. The output side of
the digital port must be driven explicitly with a quasi-continuous assignment
or equivalent (see following section for an example).
When a connect module containing a digital input or output port (i.e. with a
unidirectional digital port), no segregation takes place. In this case, the
drivers can be accessed by reading (for an input port) and the receivers can
be driven by writing (for an output port).
8.10.6
- correct figure: replace "e2c" with "c2e"
- replace body by:
The example shown in Figure 8-13 shows a connect module inserted on a
mixed net with two digital drivers, one digital load, and an (analog)
capacitative load. A bidirectional connect module that accurately models
the effects of multiple drivers is given below.
<<existing Figure 8-13 goes here>>
The c2e connect module makes use of driver access functions and mixed
domain access. The module configures the analog driving impedance
depending on the number of active digital drivers. Different drive
impedances can be used for 0 and 1 levels. In the example of Figure 8-13,
in conjunction with the load capacitor, this models rise and fall times
that are a function of the capacitance as well as the number of active
drivers and their levels.
connectmodule c2e(d, a);
cmos1 d; inout d;
electrical a; inout a;
reg out;
ground gnd;
electrical rail;
branch (rail,a) pull_up; branch (a,gnd) pull_dn; branch (rail,gnd) power;
parameter real r0 = 120.0, r1 = 100.0, roff = 1e6;
parameter real vt_hi = 3.5, vt_lo = 1.5, supply = 5.0;
integer i, num_ones, num_zeros;
assign d = out; // drive the receivers on the mixed net
// count active drivers & configure analog output section
analog begin
@(driver_update(d)) begin
num_ones = 0;
num_zeros = 0;
for(i = 0; i < driver_count(d); i = i + 1)
if(driver_state(i) == 1'b1) num_ones = num_ones + 1;
else if(driver_state(i) == 1'b0) num_zeros = num_zeros + 1;
end
// analog drivers, configured according to active drivers & levels
V(pull_up) <+ 1/((1/r1)*num_ones + (1/roff)) * I(pull_up);
V(pull_dn) <+ 1/((1/r0)*num_zeros +(1/roff)) * I(pull_dn);
V(power) <+ supply;
end
// monitor analog output and drive digital output accordingly
initial out = 1'b0;
always @(cross(V(a)-vt_hi, -1) or
cross(V(a)-vt_lo, +1)) out = 1'bx;
always @(cross(V(a)-vt_hi, +1)) out = 1'b1;
always @(cross(V(a)-vt_lo, -1)) out = 1'b0;
endconnectmodule
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