Subject: Theme for working session on Thursday 3/1
From: Ian Wilson (imw@antrim.com)
Date: Mon Feb 26 2001 - 16:07:21 PST
"Disciplines - Hierarchical or Flattened?"
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Disciplines have many roles within Verilog-AMS; they provide an abstract
definition of signal characteristics, a compile-time indication of the
legality of connecting different regions, a way to automate the selection
of conversion elements, a declarative unit to specify continuous nets,
ports & branches, and a way top embellish declarations of discrete
nets and ports.
When multiple disciplines are present in an AMS design, there must be
rules to determine how these are interpreted and if conversion elements
are inserted, where these are placed and how they are named.
There are two schools of thought on this. These can be summarized as:
H[ierarchical] Port and net declarations take priority.
F[lat] Primitive instances take priority.
To exaggerate, in the hierarchical scheme the port declarations of a
module are interpreted literally: if a module port has continuous
discipline, then that's what's inside the module. In the flattened
scheme if there's a resistor inside the module then even if the module
port declared as a wire, it's a continuous port.
The intention of Thursday's meeting is to provide a forum where these
views can be presented, with their pros and cons, and discussed in the
light of any use models that people may have. These can include, but
are not limited to: issues of net resolution, representing multi-level
logic, backannotation to connect modules, accuracy of modeling mixed
nets.
The Flattened view will be championed by Ian Wilson (Antrim). I am
hoping that Jon Sanders (Cadence) will champion the Hierarchical view.
--ian
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