Subject: one for initialization bucket.
From: Martin O'Leary (oleary@cadence.com)
Date: Wed Feb 28 2001 - 19:05:15 PST
Ian,
can you add this issue to the initialization issue bucket.
We plan to send out a proposed solution on this one too.
Thanks,
--Martin
Initialization problems with @cross in Verilog-AMS/Verilog-A
...........................................................
a. Consider the following Verilog-AMS module;
Let's assume that user needs to initialize the value of digital real
variable "T" with the V(out). Note the initialization algorithm specified
in Cadence Issue 29 (42) is assumed.
module foo1 (out);
electrical out;
real R, T; //Digital-owned variables
initial begin
R = 5.0
T = V(out);
end
always
@cross(V(out)-2.5,1) begin
T = V(out);
end
analog begin
V(out) <+ R;
end
endmodule
Digital executes at t=0 ..............T = 0.0 R = 5.0 V(out) = 0.0
V(out) is initialized to 0.0; @cross is not triggered, so behavior in
the always block is not executed.
Analog computes its first DC ........ T = 0.0 R = 0.5 V(out) = 0.5
Though V(out) changed from 0.0 to 5.0; @cross is not triggered because
@cross is ignored during DC.
Thus, at the end of initialization process, "T" continues to be "0.0"
and not "5.0" !!
To make this module work correctly it would need to be rewritten is
a more cumberson fashion by the introduction of an @timer and an
additional if(V(out))-statement to account for the timer(0) triggering.
I believe that this makes it more difficult to write robust models.
module foo1 (out);
electrical out;
real R, T; //Digital-owned variables
initial begin
R = 5.0
T = V(out);
end
always
@(timer(0) or cross(V(out)-2.5,1)) begin
if (V(out) > 2.5)
T = V(out);
end
analog begin
V(out) <+ R;
end
endmodule
If cross triggered at t=0 if V(out) > 2.5 then the model would be more
natural as the initial formulation of the model would work just fine.
b. Consider the example of a Verilog-A inverter;
module not_gate(in, out);
input in;
output out;
electrical in, out;
real vout;
analog begin
if (V(in) > 2.5) vout = 0;
else vout = 5;
@(cross(V(in) - 2.5,0);
V(out) <+ vout;
end
endmodule
It seems more natural to me to try to write the analog block as follows;
module not_gate2(in, out);
input in;
output out;
electrical in, out;
real vout;
analog begin
@(cross(V(in) - 2.5,1) vout = 0;
@(cross(V(in) - 2.5,-1) vout = 5;
V(out) <+ vout;
end
This formulation is more compact and easier to understand. However it will
not work correctly as the output voltage is not set correctly until
the cross statement triggers (some time after DC).
However it would work correctly if the cross had the capability to
trigger at time zero.
c. In existing modules, cross is used for two purposes
When I looked some Verilog-A models that use @cross, I noticed that @cross
has two distinct usages. The first usage is time-step control. The second
usage is signal-crossing detection.
An example of the time-step-control usage is the not_gate given above.
The not_gate is modelled to be a level sensitive device. Its behavior
is dependent on the levels of the inputs rather than edges in its input
signals.
The only reason @cross is used is because of the simulation algorithm.
The model wants to ensure that the simulator has a time step when the
level changes so we can recalculate the output. Looking at it another
way - if there was such a thing as analog synthesis, the @cross should
be ignored by the synthesis algorithm because it isn't necessary to
describe what an not gate does.
Using the @cross for modelling level sensitive devices means that
the user has to account for initialization of the device. This
inevitable makes the description more complex. Compare not_gate
to not_gate2
An example of the signal-crossing detection usage is a frequency
meter. The description of its behavior is that it counts the number of
times a signal cross 0V in a fixed period of time. The number of
times this crossing occurs is directly proportional to the frequency.
A line of code from the frequency meter could be;
@ ( cross (V(vp,vn),0,1.0, vp.potential.abstol) ) begin
numcrossings = numcrossings + 1;
end
Here the @cross is a fundemental aspect in the description of the frequency
meter. It should not trigger at DC because that would be incorrect behavior.
The @cross is necessary part of the behavioral description no matter what
simulation algorithm is used.
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