Subject: Re: your question about digital variable access
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Mar 16 2001 - 09:24:45 PST
Martin O'Leary wrote:
>
> Ian,
>
> In the last meeting you gave a similar example as the following
>
> module mixed1(clk,vout);
> wire clk;
> electrical vout;
>
> integer np; initial np =0;
>
> always @(posedge clk)
> np = np + 1;
>
> analog V(a) <+ np;
>
> endmodule
>
> I understand the question you posed was what values of 'np' should be seen
> in analog block and when.
>
> In terms of accessing digital variables in the analog block, section
> 8.3.6.4 of the LRM;
>
> In this case, a digital primary (reg, wire, integer, etc.) whose value is
> calculated in the discrete domain appears in an expression which is in the
> analog context; thus the analog primary is evaluated in the continuous
> domain.
>
> The expression shall be evaluated using the digital value
> calculated for the greatest digital time tick which is less than or equal
> to the analog time when the expression is evaluated.
>
> This approach does not give very predictable behavior for V(a). Basically
> the value of V(a) depends on how large a time-step analog takes. In a
> analog circuit with large time constants, the value of np that analog
> sees could be very old.
I've covered some of this before; it's unpredictable because it's a bad
way to look at time in a mixed signal simulator. If you consider time as
a single (global) entity which only advances, then it's easier to describe
the mixed signal behavior - i.e. "digital" time is a view of the global
(real & continuous time) not a seperate entity. The analog process view
of a "digital" value is just the value it has at the (global) time of
asking.
See -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/schd_sm.pdf (last sec.)
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0001/fllwup-1.html
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0005/index.html
Kev.
> If the model is rewritten such that the analog block is made sensitive to
> np, it is clearer what the value of V(a) will be as the "@np" ensures that
> an analog time-point will occur when np changes and hence that V(a) will be
> updated when np changes.
>
> module mixed2(clk,vout);
> wire clk;
> electrical vout;
>
> integer np; initial np =0;
>
> always @(posedge clk)
> np = np + 1;
>
> analog begin
> @np;
> V(a) <+ np;
> end
>
> endmodule
>
> However because module mixed1 gives such unpredictable behavior, I believe
> that the LRM should be changed so that adding the event control is not
> neccessary to get predictable results.
>
> To this end I propose we change 8.3.6.4 of the LRM to the following.
>
> In this case, a digital primary (reg, wire, integer, etc.) whose value is
> calculated in the discrete domain appears in an expression which is in the
> analog context; thus the digital primary is evaluated in the continuous
> domain.
>
> The expression shall be evaluated using the digital value
> calculated for the greatest digital time tick which is less than or equal
> to the analog time when the expression is evaluated.
>
> If the digital primary's value changes during subsequent digital time ticks
> which are less than or equal to the analog time when the expression the
> was last evaluated, the analog solution must be recalculated using the
> new digital primary value.
>
> --Martin
-- National Semiconductor 2900 Semiconductor Drive, Mail Stop D3-677, Santa Clara, CA 95052-8090
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