Subject: RE: Related Question [Re: your question about digital variable access]
From: Ian Wilson (imw@antrim.com)
Date: Mon Mar 19 2001 - 16:15:58 PST
I'm reassured that everyone sees the problems inherent in the
example (repeated below) - especially since this is by no
means a pathological case, but was taken from a 'simple'
tutorial example in a connect module.
The correct solution, in my view, is to take the position that
if you replace each occurrence of a 'wrong domain' entity with
an explicit conversion element, then the two representations of
the problem should return the same result. There are several
alternative ways to think about this - the simplest is to recognize
that when you need to access a variable of one domain from another,
that both domains must agree about what time it is. As Kevin says,
there are several ways to implement this, but we are not concerned
with that here.
Applying this to the original example:
module mixed1(clk,vout);
wire clk;
electrical vout;
integer np; initial np =0;
always @(posedge clk)
np = np + 1;
analog V(a) <+ np;
endmodule
this can be formally rewritten as:
module mixed1(clk,vout);
wire clk;
electrical vout;
integer np; initial np =0;
always @(posedge clk)
np = np + 1;
integer anp; // analog representation of np
digital_to_analog(anp, np);
analog V(a) <+ anp;
endmodule
The digital_to_analog operation provides the mixed-signal
synchronization that ensures that changes to np result in a
synchronization event between the analog and digital world,
and for a transfer of data between np and anp.
The synchronization necessary in all the cross-domain cases
can be deciphered by rewriting similarly. The problem is to
find words that express the required semantics accurately.
--ian
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