Subject: Workgroup status
From: Ian Wilson (imw@antrim.com)
Date: Wed Mar 21 2001 - 11:41:24 PST
[This is later than promised - got behind on work stuff and more
recently have been battling the dreaded 'flu. Sorry about that.]
I think that working on the following topics ('bins') for 2.1 makes
sense:
- mixed signal initialization and simulation cycle (including
alignment with VHDL-AMS semantics)
- semantics and synchronization of cross-domain access
- connect module details - $netresolve, etc
- SPICE migration path
- hierarchical vs flattened approach to nets, disciplines, etc
I know that there are other topics that have been discussed, in
particular:
- backannotation
- new parameter mechanisms for sweeps, etc
- syntax changes for connect modules, Laplace/Z filters, etc
but I would suggest that these remain as proposals for 2.1.
For completeness, note that we have agreed to postpone most of the
work on Verilog-2000 compliance and PLI until post-2.1.
The people who appear to be currently active are:
Martin, Jon (Cadence)
Sri & Graham (Motorola)
Kevin (National)
Dan (Synopsys)
Peter & Ian (Antrim)
Working groups should (ideally) consist of people from more than one
company. Their deliverables are proposed modifications/enhancements
to the 2.0 LRM to improve portability and reduce ambiguities. The scope
of these deliverables should be on the order of 1-2 months; the 2-weekly
meetings will continue but should just be quick status updates from the
work groups plus any general business that arises.
Suggestion for work group setup:
1. (initialization/simulation cycle): Peter, Dan
2. (cross-domain sync/semantics): Martin, Graham, Ian
3. (connect modules): Sri, Dan
4. (SPICE migration): Jon, Kevin
5. (net/discipline views): Ian, Jon, Kevin
As always, any feedback on the topics on which to work, and people
who should work on them, is gratefully accepted. Please remember that
we have limited assets in terms of volunteer effort and calendar time.
Thank you.
--ian
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