Subject: (no subject)
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Tue May 08 2001 - 18:46:52 PDT
Reply To: schandra@asc.corp.mot.com
Organization: Motorola Australia Software Center
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Ian,
I thought I had sent this mail last week, but realized that i hadnt
when i saw the mail from your end...
Regards,
Sri
Hi all,
I have been working with Graham on resolving the Discipline resolution
algorithm to address the issue when Analog & Digitial primitives
are instantiated in the Verilog-AMS model. The current resolution
algorithms do not handle these primitive ports.
I am also working on the timer/cross events issue with regards to
the scheduling mechanism of these events, so that there is uniformity
in calculating the dynamic expressions in these events. The proposal
gets rid of some of the ambiguity that currently exists in the
scheduling mechanism. I will post that one some time during next
week.
This mail includes the Problem, Analysis, and a Proposal for
the discipline resolution (which addresses the problem of primitives).
After discussions, we can probably reword the proposal in a more
formal manner to fit in to the LRM.
Thanks and Regards,
Sri
ACRONYMS:
---------
DR -- Discipline Resolution
digital primitive -- gate/switch -level Verilog and user-defined
primitive
analog primitive -- spice device
PROBLEM:
--------
The DR mechanism (defined in section 8.4 [LRM]) defines two alternative
methods to resolve nets with unspecified disciplines based on it
instance interconnections. This DR mechanism relies on knowing the port
discipline of each port connection that the net is connected to.
Therefore Verilog-AMS/Verilog/Verilog-A module instantiations can be
handled, however digital and analog primitive instantiations do not have
a discipline associated with its ports.
The following proposal defines a method to allow the DR mechanism to
process the entire module hierarchy (including primitive instantiations)
in order to resolve a net without a specified discipline.
ANALYSIS:
---------
An argument can be put forward that analog primitive ports always use
"electrical" discipline and similarly digital primitive ports always use
"logic" discipline. This argument exploits only the second
characteristic of primitives defined below:
- Primitives define generic behaviour only (primitive instantiations
overrides then customises it for a particular use or technology
(in particular digital primitives, less so for analog primitives).
- Primitive behaviour is generally restricted to a single technology
or discipline. (Digital primitives do not model mixed technology
behaviour internally. Analog primitives are primarily defined for
electrical circuits, but some are generic across other disciplines.
This argument works for digital primitives for now, because a digital
primitive is compatible with any other digital primitive. If in the
future, technology based disciplines are defined, then this argument
breaks down. Also, if analog primitives are restricted to electrical
models only, the argument works. But this constraint goes against the
goals of the Verilog-AMS LRM. Specifically:
1. The symmetry of digital primitive usage scope in the Verilog
language subset is different to the analog primitive usage scope
in the Verilog-A subset. Another inconsistency a Verilog-AMS
modeler has to be aware of.
2. To re-iterate the above point further, the Verilog-A language
subset is multi-disciplinary language (see section 1 [LRM]), this
argument restricts language capability and limits the generic
spice device behaviour that already exists.
3. If analog primitives are made to be generic across all disciplines
then the electrical discipline must be compatible with all other
continuous disciplines. This undermines the net/discipline
compatiblity rules in section 3.8 [LRM].
Based on the above a more general solution can be adopted that avoids
the above negative aspects and exploits both characteristic of
primitives. ie Primitive ports have no inherent discipline, but it has a
inherent domain. For example, analog primitives is defined to have
analog ports, while digital primitives are defined to have digital
ports.
During DR processing an analog port is compatible with any continuous
primitive discipline, while a digital primitive port is compatible with
any discrete discipline. During post-DR processing, all the connecting
nets of a primitive instantiation can be checked for compatiblity with
each other.
PROPOSAL:
---------
The DR mechanism can be easily updated to handle this more general
solution with little conceptual change to the Verilog-AMS language and
minimal pyshical change to the [LRM].
First, allow the Verilog-AMS modeler to specify the disciplines that a
particular primitive instantiation will use through the modified DR
rule statement.
The discipline_list (disciplines left of the 'resolveto' keyword) refer
to the disciplines of the ports that connect to the net. To handle
analog and digital primitive ports, two additional keywords are added to
represent primitive ports they are:
- 'analog' keyword, for analog primitives. this keyword is
compatible with any continuous discipline in a discipline resolution
rule's discipline list.
- 'digital' keyword, for digital primitives. this keyword is
compatible with any discrete discipline in a discipline resolution
rule's discipline list.
When resolving an unspecified net's discipline and a digital primitive
port connection is detected, it will be matched with any 'digital'
keyword within the discipline resolution rules being processed.
Likewise, when an analog primitive port connection is detected, it will
be matched with any 'analog' keyword in the discipline resolution rules
being processed.
The second modification to the [LRM] is with respect to implied
"self-resolution" rules in the discipline resolution rules. A
"self-resolution" rule is interpreted to be when a one or more identical
disciplines is always resolved to itself. for example:
connect electrical resolveto electrical;
connect logic resolveto logic;
Similar for all other continuous and disciplines defined in a
Verilog-AMS model. However 'analog' and 'digital' cannot be automatic
self resolved without additional external information. In example below,
implicit nets 'n1' and 'n2' cannot be resolved without primitive self
resolution rules.
module x;
nand inst_1(n1, ...);
and inst_2(..., n1, ...);
resistor #(...) inst_3(..., n2);
resistor #(...) inst_4(n2, ...);
endmodule
To avoid such behaviour the following self-resolution rules will need to
be defined within 'connectrules' blocks in the Verilog-AMS model.
connect analog resolveto electrical;
connect digital resovleto ttl;
This allows Verilog-AMS modeler to specify the discipline of the analog
and primitive ports.
Below: is the modified syntax for discipline resolution rule. (Note:
text in upper case represents lowercase Verilog-AMS keywords).
connect_resolution ::=
CONNECT discipline_list RESOLVETO discipline_identifier ;
discipline_list ::=
discipline_identifier
| ANALOG
| DIGITAL
| discipline_list, discipline_identifier
REFERENCES
----------
LRM -- Verilog-AMS LRM version 2.0 (18 Feb 2000)
Thanks and Regards,
Graham & Sri
-- Srikanth Chandrasekaran EDA Solutions and Products SBU Phone: +61-8-8203 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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