Subject: Re: Proposal for rewriting Section 8.3.2
From: Martin O'Leary (oleary@cadence.com)
Date: Wed Oct 31 2001 - 14:08:50 PST
Sri,
before we discuss this proposal on tomorrow, could you outline the
reasons why you want to change section 8.3.2??
Also could you outline the specific changes you want to make,
desirably in terms of impact.
As I mentioned in my previous email, there is a typo in a paragraph
in 8.3.2 which should read;
"All operators, functions and statements which are allowed in continuous
context,
except for case-equality, case-inequality, case, casex, casez,shall
report an error if the expressions they operate on contain x or z bits".
With this ammendment, what other issues do you have with 8.3.2?
In terms of your proposal I have included comments in the attached message.
Thanks and talk to you tomorrow,
--Martin
On Oct 29, 1:55pm, Srikanth Chandrasekaran wrote:
> Subject: Proposal for rewriting Section 8.3.2
> Hi Committee Members,
> We have worked a proposal for rewriting section 8.3.2 which refers to
>
> Proposal:
> =========
> --------------------------------------------------------------------------------
>
> 8.3.2 "4-state logic processing in continuous context"
>
> The Verilog-AMS HDL provides limited support for accessing and comparing
> 4-state-logic values in the analog context. The following operands
> return 4-state-logic values:
>
> * digital net access (section 8.3.1)
> * binary, octal, hexadecimal numbers (section 2.5).
>
> When the above operands are used in analog context expressions,
> 4-state-logic to integer values conversion are performed (section 8.3.1)
> when the expression is solved.
>Processing of 'x' and 'z' states is
> vendor specific.
In the ammended 8.3.2, this is defined as erroreous unless such states
are being operated on by case[xz], ===, !===. In the committee we decided
to be restrictive in this way so that X, Z access in the analog block could
be liberalize in the LRM at some later point without concern for breaking
existing modules at that point. Changing 8.3.2 so that "Processing
of 'x' and 'z' states is vendor specific" defeats this intent.
>
> Comparisons of 4-state logic values are limited to case, casez, casex
> statements (section 6.5). All other analog context comparison
> operators (ie. ===, !==) and statements (ie conditional) use real and
> integer types only.
In the 8.3.2 (ammended and unammended) suggests that ===, !==,
case[xz] can be used to operate on 4-state expressions. In the proposal
'===', '!==' were removed from that list. Can you explain why?
>
>
> Example:
> input net[1:2];
> analog begin
> case(net[1])
> 1'b1: $strobe("net[1] = 1");
> 1'b0: $strobe("net[1] = 0");
> 1'bz: $strobe("net[1] = z");
> 1'bx: $strobe("net[1] = x");
> net[2]:$strobe("net[1] == net[2]");
> endcase
> end
>
> If "net" is discrete, the "1'bx" and "1'bz" cases are solved without error.
> If the "net" is continuous then the processing of the "1'bx" and "1'bz" cases
> will be vendor specific.
If a net is continuous, the above code is erroreous. Section 5.1.1
states that; "Flows and potentials on nets, ports, and branches are accessed
using access functions."
The value of "net" is not accessed using an access function.
Another question I have is how could "net" become continuous?
Based on the usage of "net" above, when a simulator is resolving the
domains of nets in a circuit, it should assume that "net" is discrete.
Thanks,
--Martin
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