Subject: Re: Next LRM Committee call
From: Kevin Cameron (dkc@galaxy.nsc.com)
Date: Thu Nov 15 2001 - 16:33:00 PST
Srikanth Chandrasekaran wrote:
> Hi Committee Members,
>
> Could we have the next committee meeting call on Nov 22nd, 3:30pm PST.
> We will go through the set of slides that was discussed in the call, which
> would mainly address the "Discipline Resolution" issue.
22nd is OK with me.
Note: there are two types of "Discipline Resolution": a) working out which
discipline
applies to the net as a whole to determine attributes for analog simulation, and
b)
which discipline is used for A/D insertion. I presume we are discussing the latter
and
associated issues of A/D placement etc.
If someone sends me the slides I'll put them on the web-site.
See also:
Issue 3: A/D Convertor placement
Follow-up 2 2: Driver-receiver Segregation
> We got some kind of closure on "Section 8.3.2" about which the meeting minutes
> were sent after the call, with some follow-on comments.
[I think my last comment on that might have gotten lost.]
Your e-mail implies that it would be a runtime error to assign X/Z to a variable
even
if that variable is not used in a branch assignment. I think that will be
unworkable in
practice as many synchronous logic circuits will generate X & Z values while
changing
state, but will expect those values not to propagate because they do not occur at
clock
edges or while gating signals are active. Verilog-AMS should not fail (with a
runtime error)
unless an X or Z derived value is actually used in a branch assignment.
Regards,
Kev.
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