Subject: Re: Disciplines & A/D conversion
From: Kevin Cameron (dkc@galaxy.nsc.com)
Date: Fri Nov 16 2001 - 11:21:58 PST
Jon's presentation:
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/CDN_Disc.ppt
[Let me know if you have problems downloading it.]
My view of how the digital/analog shared nets should be handled is that it
is just an extended form of signal resolution, i.e. there is no "segmentation"
of a net through the hierarchy, there is a single node which has multiple
drivers and receivers some of which are analog and some are digital, and
the simulator "resolves" all driving values to a single value for the node
and then distributes that to the receivers. Verilog-D works that way
(ignoring hierarchy) when resolving multiple digital drivers. When the
drivers of a net belong to different domains, we insert convertors to
convert the lower accuracy domain drivers to the higher accuracy
(digital to analog), and resolve in the higher accuracy domain. The
split & merged attributes in connection rules indicate whether (digital)
drivers can be considered as a group rather than individually.
The current LRM describes (as in Jon's presentation) a scheme in which
the A/D conversion elements are bound to ports, but it is not entirely
clear what the complete semantics are when there are alternating layers
of analog and digital port definitions.
I think there are two approaches that make sense a) port-bound, which
groups drivers by hierarchy and places A/D converters at the port,
and b) process-bound which entirely ignores the hierarchy and inserts
A/Ds as close as possible to the driving(/receiving) processes. The
former is more-or-less what we have now and applies when a port
marks a physical boundary which is not represented in the design
structure e.g. if you have an RTL design that you decide split into
multiple FPGAs on a board, port-bound D2As would be used to
model the FPGA pads so that the board-level simulation is accurate
(the internals of the FPGA would probably be pure Verilog-D and
out-going drivers would be merged). The process-bound approach
applies where ports have no physical significance e.g. inside a
(mixed signal) ASIC where there are only simple wires between
the active components, and hierarchy is only a rough indicator of
proximity.
The "split" vs. "merged" handling of drivers and receivers is not
necessarily more or less accurate one way or the other, all designs
could be done with "split" and "process-bound" semantics, but that
would be somewhat inefficient in simulation as it creates the most
A/D connect modules. In the case where the drivers are of the
same type e.g. board level standard CMOS/ECL/TTL it is more
efficient to lump the calculation, and not implicitly less accurate,
the calculation is likely to be less accurate in an ASIC where
the driver strength is different in every cell only because we havn't
added access to the cell/driver attributes through the driver access
functions. Similarly, bidir connection modules were introduced just
as a another mechanism for speeding up the net resolution calculation.
Hope this helps.
Kev.
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