Subject: Re: Auto insertion of interface elements
From: Jonathan Sanders (jons@cadence.com)
Date: Sun Dec 02 2001 - 13:14:31 PST
Am trying to send this again as it got bounced on the reflector. If you
have problems opening it let me know.
Jon
> Peter,
> I have appended a set of slides that hopefully answers your
> question. Since your example resulted in no different between split and
> merged I also modified your example to show how split would come into
> play. Rather than using the current LRM with respect to digital
> primitives I assumed that we would change the LRM to allow CMs to be
> connected to them so these slides account for that. Let me know if this
> helps or does not help.
> Jon
> P.S. next week we have a user group meeting so my availability will likely
> be after hours.
At 10:45 AM 11/28/2001, Peter Liebmann wrote:
>In trying to figure out how interface elements are inserted via the 4
>methods given in the LRM (detailed split and merged and default split and
>merged) I came up with a problem which Don and I are totally confused about.
>
>The following circuit is the top level contains a digital clock and an
>instantiation of a module which instantitates an analog inverter and another
>module which instantiates a digital inverter and another module ...etc.
>
>Jon - could you please tell me where the interface elements are inserted for
>the different methods?
>
>This case is (at present) our biggest stumbling block in understanding the
>LRM.
>
>Here is the netlist:
>
>`include "constants.h"
>`include "disciplines.h"
>`include "connect.h"
>`timescale 100ns / 10ns
>
>module top;
> reg clk;
>
> lev1 l1(clk);
>
> initial
> clk=0;
>
> always
> #10 clk=~clk;
>
>
>endmodule /* top */
>
>module lev1(clk);
> input clk;
> lev2 l2(clk);
> a_inv a1(clk);
>endmodule /* lev1 */
>
>module lev2(clk);
> input clk;
> lev3 l3(clk);
> d_inv i1(clk);
>endmodule /* lev2 */
>
>module lev3(clk);
> input clk;
> lev4 l4(clk);
> a_inv i1(clk);
>endmodule /* lev3 */
>
>module lev4(clk);
> input clk;
> d_inv i1(clk);
>endmodule /* lev4 */
>
>
>module d_inv(clk);
> wire out,clk;
> input clk;
>
> not (out,clk);
>
>endmodule /* d_inv */
>
>module a_inv(clk);
> electrical clk,out;
> input clk;
> integer step;
> analog begin
> @(cross(V(clk)-2.5))
> step = ~step;
> V(out)<+transition(step);
> end
>endmodule /* a_inv */
>
>--
>Peter Liebmann
>
>Antrim Design Systems, Inc.
>Tel. 831-430-4804
>Fax. 831-430-1904
***********************************************************
Jonathan L. Sanders
Product Engineering Director
Custom IC Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7265
***********************************************************
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