Subject: Re: Proposal for Section 8.3.2 based on LRM Committee discussions
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Thu Jan 24 2002 - 17:02:37 PST
> From: "Srikanth Chandrasekaran" <schandra@asc.corp.mot.com>
>
> Hi all,
> Following is the proposal for rewriting Section 8.3.2, to remove some of the apparent
> ambiguity of accessing 4-state logic in analog context, through discussions from the
> LRM calls on 5th Nov 2001.
>
> Kevin,
> You had sent some followup mails regarding X & Z following the call. I have written this
> proposal based on what we discussed during the call and we could go from here.
More below...
> Section 8.3.2: Accessing discrete nets in Continous Context
> -----------------------------------------------------------
>
> 4-state logic values can be access within analog context. The x and z
> states must be translated to equivalent analog real or integer values
> before being used within the analog context. The case, casex, and casez
> statement and ===, !== operators provide a mechanism to perform this
> conversion.
Making users translate Xs & Zs prior to use in an analog block is
impracticable, I presume you just mean they must be translated before
assignment to a branch or real value?
> Example:
>
> module a2d(dnet, anet);
> input dnet;
> output anet;
> logic dnet;
> wire dnet;
> electrical anet;
>
> analog begin
> case (dnet)
> 1'b1:var = 5;
> 1'bx:var = var; // hold value
> 1'b0:var = 0;
> 1'bz:var = 2.5; // high impedance - float value
> endcase
> V(anet) <+ var;
> end
> endmodule
>
> Note: case statement may be replaced with if-else-if statement using the case
> equality operators to perform the 4-state logic value comparisons.
>
> Accessing digital net and digital binary constant operands are supported within
> analog context expressions. It is an error these operands returns 'x' or 'z'
> bits values when solved. It will be an error if the value of the digital
> variable being accessed in the analog context goes either to 'x' or 'z'.
I.e. it is a runtime error, but what is being checked? General logic expressions
need to be evaluated in order to test for Xs and Zs, and it may be valid to
ask if "1'bx == 1'bx" (which you list as an error below).
I think it would be better defined as:
It is illegal to assign an X or Z to a branch, real or integer in an analog
context.
That makes the RHS evaluation the same in both analog and digital with respect
to logic values.
> Example:
>
> reg dnet;
> electrical anet;
> integer var1;
> real var2;
>
> initial begin
> dnet = 1`b1;
> #50 dnet = 1`bz;
> $finish;
> end
>
> analog begin
> var1 = 1'bx; // error
> var2 = 1'bz; // error
> var1 = 1 + dnet; // error after #50
> var2 = 0.35 + dnet; // error after #50
>
> if(dnet == 1'bx); // error
> V(anet) <+ 1`bz; // error
> V(anet) <+ dnet; // error after #50
> end
>
>
> --
> Srikanth Chandrasekaran
NB: I still don't like assignments that may not be used causing errors. If
I write code like this:
real v1,v2;
v1 = logic_a * 2.0;
v2 = logic_b * 3.0;
if (logic_c)
V(out) = v1;
else
V(out) = v2;
- I don't want it to fail when logic_c is 1 logic_a is 1 and logic_b is X.
So I would still rather have:
X or Z are considered as NaN when promoted real. NaN, X or Z cannot be
recast as integer or assigned to a branch, attempting to do so will
cause a runtime error.
Kev.
----
This archive was generated by hypermail 2b28 : Thu Jan 24 2002 - 17:04:06 PST