Re: Status Report For Accelera Board Meeting

Subject: Re: Status Report For Accelera Board Meeting
From: Sri Chandra (schandra@asc.corp.mot.com)
Date: Sun Feb 03 2002 - 17:22:51 PST

Meeting Minutes for LRM Committee call held on 28th Jan 2002.
Attendees: Peter, Don Webber (Antrim), Kevin (National Semiconductor), Jon, Martin (Cadence), Graham, Sri (Motorola)

Status of various issues being addressed were discussed

Issue 1: Discipline Resolution problem. (There are various related issues that are being discussed as part of DR, and a number of spin-off issues to resolve this problem. Some of the subissues may not be addressed in the next version and might have to be postponed.)

SubIssue 1:  Proposals for removing ambiguity on connect-resolveto as specified in Section 8.7.2
(Syntax: connect <discipline_list> resolveto <resolved_discipline>)
Status: There was an agreement that there is ambiguity in the semantic rules for connect-resolveto statements.
Action (Sri): To send a rewrite of 8.7.2 which would close the current holes in the rules of these statements. This to be done by Feb 9th 2002.

SubIssue 2: Proposal for reinclusion of digital port names for instantiating digital primitives. This port name shall only be used to create unique instances for a connect module, and to access specific instance. This instance name shall not be used as a mechanism for named port connections while instantiating digital primitives.
Status: Jon has sent a proposal for digital port name inclusion. Kevin to send alternate naming convention (done already).
Action: This would be discussed in next call.

SubIssue 3: Inherited Connection proposal used by Cadence
Status: Jon yet to hear from cadence legal before posting it to the LRM committee mailing list.
Action (Jon): To post the proposal once cleared by Cadence.

SubIssue 4: Overriding default_discipline for the analog/digital primitives on an instance-by-instance basis
Status: Martin & Jon are working on this proposal.
Action (Martin/Jon): To send proposal by end of this week and would be discussed in next call (11th Feb 2002).

SubIssue 5: Reference to derived disciplines in LRM examples without supporting BNF syntax.
Status: Not clear yet. No change in status. Has to be decided whether this is going to be addressed in the next version of LRM.
Action: None

SubIssue 6: Port vs Process Bound approach for Discipline Resolution.
Status: Antrim was working on a proposal sometime back but not much has happened recently. No change in status.
Action: None

Issue 2: Proposal for re-writing Section 8.3.2 (4-state logic, X & Z bits access in analog context)
Status: A proposal has been sent by Sri on Jan 25th 2002 based on the discussions, which might be included in next version and voted upon.
Action (Sri): Have been completed and proposal posted.

There are couple of other issues that was discussed sometime back but hasnt been taken up in recent calls. Need to decide on status of these and when it would be addressed.

Issue 3: Real valued ports & real net declaration semantics in the LRM.
Status: This issue was taken up to be in sync with Verilog++ / System Verilog. Apparently this is not being driven by the Verilog++ committee. Not clear as to how this is going to be addressed. No change in status.
Action: None

Issue 4: Parasitic Back Annotation issue.
Status: Proposals have been sent/resent by Kevin in the past.
Action: ??

Thanks & Regards,
Sri

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