Subject: AMS Data & Simulation Model Update
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Mar 01 2002 - 15:20:57 PST
For those of you only on the V++ mailing list, this
document is an attempt at describing a mixed signal
simulator abstractly, so that we can fit the language
to it.
http://www.eda.org/verilog-ams/htmlpages/vams_obj.pdf
There is some overlap between SystemVerilog and Verilog-AMS
in the introduction of new data types, so I added some notes
on SystemVerilog interoperability - the use of "wreal" vs.
"real".
Regards,
Kev.
-- National Semiconductor 2900 Semiconductor Drive, Mail Stop A1-520, Santa Clara, CA 95052-8090
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