Subject: Re: AMS Data & Simulation Model
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Mon Apr 08 2002 - 18:40:20 PDT
The Verilog-? abstract model (VAM) document...
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For those of you only on the V++ mailing list, this
document is an attempt at describing a mixed signal
simulator abstractly, so that we can fit the language
to it.
http://www.eda.org/verilog-ams/htmlpages/vams_obj.pdf
There is some overlap between SystemVerilog and Verilog-AMS
in the introduction of new data types, so I added some notes
on SystemVerilog interoperability - the use of "wreal" vs.
"real".
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Vs. Section 8:
A VAM process is similar to "context" in section 8, the difference
is that "context" overlaps with "driver" and "view", it therefore
fails to represent boundary (A/D converter process) properly.
Section 8 also lumps ports with nets, nodes and signals, which is
(IMO) incorrect as ports are purely a syntactic construct and have no
physical significance, but have become confused with drivers.
If anyone thinks my VAM is incorrect or deficient, I'll be happy
to amend/justify it.
Note: it is important to have the right model for this because bad
semantics will cause real problems from a simulation and hardware
modelling perspective when we try to merge the SystemVerilog
"interface" construct and user-defined types.
Kev.
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