Subject: Proposal for Section 8.3.2 based on LRM Committee discussions
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Mon Apr 15 2002 - 19:46:32 PDT
Hi all,
Following is the proposal for rewriting Section 8.3.2, to remove some of the
apparent ambiguity of accessing 4-state logic in analog context, through
discussions from the LRM calls.
Section 8.3.2: Accessing discrete nets in Continous Context
-----------------------------------------------------------
4-state logic values can be access within analog context. The x and z
states must be translated to equivalent analog real or integer values
before being used within the analog context. The case, casex, and casez
statement and ===, !== operators provide a mechanism to perform this
conversion.
Example:
module a2d(dnet, anet);
input dnet;
output anet;
logic dnet;
wire dnet;
electrical anet;
analog begin
case (dnet)
1'b1:var = 5;
1'bx:var = var; // hold value
1'b0:var = 0;
1'bz:var = 2.5; // high impedance - float value
endcase
V(anet) <+ var;
end
endmodule
Note: case statement may be replaced with if-else-if statement using the case
equality operators to perform the 4-state logic value comparisons.
Accessing digital net and digital binary constant operands are supported within
analog context expressions. It is an error these operands returns 'x' or 'z'
bits values when solved. It will be an error if the value of the digital
variable being accessed in the analog context goes either to 'x' or 'z'.
Example:
reg dnet;
electrical anet;
integer var1;
real var2;
initial begin
dnet = 1`b1;
#50 dnet = 1`bz;
$finish;
end
analog begin
var1 = 1'bx; // error
var2 = 1'bz; // error
var1 = 1 + dnet; // error after #50
var2 = 0.35 + dnet; // error after #50
if(dnet == 1'bx); // error
V(anet) <+ 1`bz; // error
V(anet) <+ dnet; // error after #50
end
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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