Subject: Re: contribution stmts in loops
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Wed May 01 2002 - 18:09:51 PDT
Hi,
I think disallowing this for now is fine. I just want to know what vendors
think and what the BNF says and whether both of them are in sink.
So related to this is another query...
module blackbox;
integer i;
genvar g;
for (i = 0; i < 10; i = i+1) begin
for (g = 0; g < 2; g = g+1) begin // should this be allowed...
...
...
end
end
endmodule
According to the BNF
'analog_stmt' (genvar for) is not part of 'stmt' syntax.
Just want to make sure the above BNF is correct and the model i have written
is syntactically incorrect
cheers,
Sri
Kevin Cameron x3251 writes:
#
#> From owner-verilog-ams@eda.org Tue Apr 30 01:19:42 2002
#>
#> Is contribution statements allowed inside repeat while conditions?
#>
#> analog begin
#> i = 2;
#> repeat (i)
#> V(a,b) <+ I(a,b) * 10; // should this be allowed?
#> end
#>
#> cheers,
#> Sri
#
#In theory anything you can unroll and the branch structure remains
#constant could be allowed. If you can't tell in advance (easily)
#then it is better to disallow a construct.
#
#In the case above the branch usage does not depend on the reptition
#so it should probably be allowed, but it is probably implementation
#dependent whether you can do it in general. As it's semantics
#rather than syntax, we can ban it for now and remove the restriction
#later if the demand is there.
#
#Kev.
#
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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