Subject: LRM Updates
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Jul 23 2002 - 15:30:56 PDT
Rehashed section 8.1 document attached plus an addition for 8.6.
BTW, here's a piece of code that's quite interesting - it uses
Synopsys's recommend style for tri-state design:
`timescale 1 ns / 1 ns
module b;
wire [0:0] b;
reg enable1,enable2;
assign b = enable1 ? 1 : 1'bz;
assign b = enable2 ? 0 : 1'bz;
initial begin
enable1 = 0;
enable2 = 0;
#1;
enable1 = 1;
#1;
enable2 = 1;
#1;
enable1 = 0;
#1;
end
always @(b) $write("b = %b\n",b);
endmodule
The assigns are actually separate drivers, so should be eligible
for separate D2A conversion. If so the auto-inserted modules
need different names, but there isn't much that distinguishes
them from each other other than declaration order.
Kev.
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