Subject: Minutes of today's meeting (19th August 2002)
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Mon Aug 19 2002 - 21:43:02 PDT
Attendees: Kevin (NSC), Don (Antrim), Martin (Cadence), Graham & Sri (Mot)
Discussion on Chapter 9 'Scheduling Semantics':
* Issue # to be stated on the proposal (Sri to send the relavent issue # to
Kevin or directly add them to the doc if the mif is available)
* Page 9-5: Instead of using quotes for the analog macro process use the
quotes only when it is defined for the first time
* Page 9-5: Use term 'analog events' instead of individually quoting the
events (1. all events are not quoted in that section and 2. needs to be
updated every time a new event is added)
* Page 9-6: Lot of discussion on whether the analog process should be sensitive or not
to changes in the digital variable.
Action: Sri to post this issue to the mail reflector
* Page 9-6: Rounding vs Truncation issue came up...Not yet resolved. Probably
needs to be resolved as part of the voting process. VHDL-AMS does truncation
so using VHDL-AMS models with Verilog-AMS has a conflict, at the same time
truncation reduces the error to half a tick when replacing analog device for
its digital equivalent.
* Figure 9-2: It will be good to include the source code for the analog
behaviour for the zero delay inverter. This would make Section 9.2.3
'The synchronization loop' more clear.
* Graham is planning to send a few more use cases on this to Kevin to fully
understand how the synchronization loop would be working.
* Lot of debate on "striking out" section 9.2.4. It was felt that it would be
good to have the section included. This section assumes dual solvers one for
digital and one for analog instead of a single mixed signal solver.
It was recommended to have this section in the document, and rework the
points so that it is consistent and correct.
cheers,
Sri
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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