Subject: Re: Updates to chapter 8
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Aug 23 2002 - 11:31:34 PDT
Srikanth Chandrasekaran wrote:
> Hi all,
>
> The following attachements include updates to the following sections in the LRM which would be discussed in the committee meetings.
>
> Section 8.3 - Rewriting "accessing 4 state logic values in the analog context" to clarify some ambiguities
> Section 8.7 - Rewriting "connect-resolveto" statements for resolving domains to clarify some of the ambiguities while using these rules.
>
Do we have a statement anywhere on how NaN is treated?
If not, I would suggest adding a new Section after 8.3:
8.X Special Floating Point Values
Floating point arithmetic can produce special values representing
plus and minus infinity and Not-a-Number (NaN) to represent a bad value.
While use of these special numbers in expressions is not an error,
it is illegal to assign these values to a branch.
Note: Verilog-D does not error on division by zero, so NaN etc can propagate
through wreal connections.
Kev.
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