Subject: Minutes of Verilog-AMS LRM call (9th Sept)
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Wed Sep 11 2002 - 00:48:20 PDT
Attendees: Sri, Graham (Motorola), Martin, Jon (Cadence)
Date: 9th Sept 2002
* The freeze date for LRM changes have been moved from Sept 16th to Sept 23nd.
* The following issues will be discussed next monday and the monday after
that. Any proposal updated in the LRM document not submitted before Sept
22nd shall not be reviewed as part of 2.1.
1. Support of instantiating digital primitives in analog blocks
2. `default_discipline usage dealing with digital and analog primitives
3. wreal issues with the current LRM
4. sychronization updates from Martin
- Issues 1, 2 have been previously submitted to the LRM committee in textual
format. However for review purposes these are to be updated in the
relavent sections of the LRM and reviewed. These two are expected to be
reviewed for 16 Sept
5. closure on the `include proposal sent by Kevin.
* The BNF for the LRM is being reworked upon because the current BNF is
1. incomplete
2. Not very clear when it comes to digital/analog definitions
- Graham has been working on reworking the AMS BNF taking into account the
current 1995 std reference for digital to come up with a more cleaner and
implementable BNF.
- It was decided that since its a fairly big cleanup it may not meet the
Sept 22nd deadline. So this will be the major activity post 2.1 release
- New updated BNF for Verilog-AMS will be released as a LRM 2.2 version
before the end of the year.
* Hope to have version 2.1 of LRM sometime in October.
Next call: 16 Sept 2002
Sri
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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