Subject: Re: scheduling semantics for Verilog-AMS (issue 25)
From: Alec Stanculescu (alec@fintronic.com)
Date: Wed Sep 18 2002 - 11:33:18 PDT
Kevin,
First, I have Verilog-AMS 2.0 LRM, but what is says makes so much
sense that I do not believe that it changed since:
8.3.6 Concurrency
.........
Any synchronization method can be employed, provided that the
semantics <is> preserved. A typical synchronization algorithm is
presented in 9.2.
8.6.3.2
...........
When it is determined <that> the event has occurred in the digital
domain, the statements under the event control shall be executed in
the analog domain at the time corresponding to a real promotion of the
digital time.
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I conclude that the analog part must be evaluated at the correct time
but not necessarily at the same delta.
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Your point seems to be that the analog part should be evaluated at the
same "delta".
However, please note that if event A occurs in the n-th delta, it does
not mean that event B that occurs in the (n+1)-th delta is dependent
upon event A, nor that in the real circuit event B should occur after
event A.
Therefore, one should use a modeling approach in which the results do
not depend on the exact delta at which an event occurs. Such modeling
style allows for faster simulation and does not hide timing problems
that may produce difficulties later on.
> You can't count on the order within a delta cycle, but you do count on
> the order of execution over delta cycles, a #0 pushes execution into the
> next delta cycle. The implication (as I read it) was that any event crossing
> the digital->analog boundary would be delayed until the last delta for a given
> time which can put it out-of-sync.
If deltas are important, then one can use #1, #2, etc. for delays in
gates, latches, etc., but such approaches must be used based on a very
well thought modeling discipline that is adequate for a given family
of circuits. This will give you control over deltas (in a sense with
#1 you make your own delta), but the delta approach may not lead to
circuits that work once the description is synthesized.
>
> [ I had problems with parallel processing digital Verilog with some designs
> if the concurrent threads were not sync'd at the delta cycle level.]
>
Such descriptions may not work well after being synthesized.
> Maybe we'll get semaphores in SystemVerilog soon and the problem will start
> going away :-)
>
Given that tasks in Verilog are re-entrant and all invocations of a
given taks share the same local variables, it is extremely easy to
code semaphores in Verilog using tasks. Indeed, semaphore-based
synchronization will work even after the circuit is synthesized.
> Kev.
>
Regards,
Alec
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