Subject: Rounding (w' VHDL)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Dec 18 2002 - 15:47:15 PST
If you are using VHDL with Verilog-A the timestep of the digital engine
is 1fs, since that
would probably have better accuracy I have no objection to changing the
text to say that
the maximum allowed error is half a tick, but the simulator is free to
do better than that.
I.e. you can always truncate on scheduling if you want to, but internal
scheduling would
be finer.
The `timescale directives only apply to the scheduling delays for
modules, and do not
dictate what the minimum timestep used by the simulator actually is,
i.e. I can say
1ns/1ns for one module, but if another is 1ns/10ps the simulator is
forced to use 10ps
scheduling.
Timescale is defined as:
`timescale time_unit base / precision base
I propose changing the text in 9.3.2.3 para 2 to:
For the purpose of reporting results and scheduling delayed future
events, the digital kernel rounds A2D event times such that error
is limited to half the precison base for the module whose port is
being connected. For the examples below the timescale is 1ns/1ns, so
the maximum scheduling error when swapping a digital module for it's
analog counterpart will be 0.5ns. A2D statements that do not
include a scheduling delay are processed immediately in a new
digital simulation cycle such that dependent zero-delay
non-blocking assigns are executed before control returns to the
analog domain.
Is that OK with everyone?
Kev.
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