RE: VERILOG-AMS COMMITTEE MEETING


Subject: RE: VERILOG-AMS COMMITTEE MEETING
From: Peter Liebmann (peterl@xpedion.com)
Date: Mon Feb 24 2003 - 11:05:53 PST


I also have a conflict. The Compact modeling meeting is Tuesday through
Thursday. I will be available on Friday.
 
Peter Liebmann
 
-----Original Message-----
From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of David W. Smith
Sent: Monday, February 24, 2003 11:00 AM
To: 'Jonathan Sanders'; 'Verilog-AMS LRM Reflector'
Cc: 'Jonathan Sanders'; Vassilios.Gerousis@Infineon.com; 'Dennis Brophy'
Subject: RE: VERILOG-AMS COMMITTEE MEETING
 
Hello Jonathan,
There is a problem with this timing. Vassilios has a TCC Chairs meeting
scheduled from 3-5 on Thursday (and there are other meetings from 8:00am
until 3:00pm on Thursday and all day Friday). Unfortunately I will not
be able to attend and neither will Vassilios (at least as far as I am
aware).
 
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
 <http://www.synopsys.com/> http://www.synopsys.com
-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Jonathan Sanders
Sent: Monday, February 24, 2003 10:28 AM
To: Verilog-AMS LRM Reflector
Cc: Jonathan Sanders; Vassilios.Gerousis@Infineon.com; Dennis Brophy
Subject: VERILOG-AMS COMMITTEE MEETING
Importance: High
Colleagues,

This week many engineers and EDA vendors will be discussion various
aspects of HDL based design using VHDL and Verilog at DVCon here in San
Jose. The Verilog-AMS committee recently completed our latest revision
(2.1) of the Verilog-AMS Accellera standard and have submitted it to the
Accellera board for approval. We are now at the point that we are in
need of your participation in both helping to drive the direction of
what is next and how to get there. For this reason we will be having a
meeting this Thursday at 3PM to kick off our next round of activities.

The meeting is currently scheduled for this Thursday, February 27th from
3 to 5 PM at Cadence just a few miles from DVCon. We understand that
some of you may not be able to attend in person (although that is
desired) so we will be having a call-in number. The call in number is
via RSVP so please send a reply back to this email and I will provide
you the call in information.

Location:
http://esds.cadence.com/education/esout.mapstock.show_map?p_map_title=CD
S-SanJoseCA_Map.gif
<http://esds.cadence.com/education/esout.mapstock.show_map?p_map_title=C
DS-SanJoseCA_Map.gif&p_session_id=20030223375248>
&p_session_id=20030223375248

555 River Oaks Parkway
San Jose, CA 95134
Building #3 (Little River Oaks Conference Room)
*Note, the above map show you directions to Building 6 which is across
the street, this campus is at the corner of Seely and River Oaks.

Topics to discuss are:

-IEEE 1364 Sync up plans
-System Verilog Sync up plans
-Additional Verilog-AMS cleanup and extensions
-Extensions for RF and MEMs
-Extensions for SPICE device model support

If you are unable to attend but desire to join the committee on a
regular basis please also let us know and we will make sure you get
properly involved. Also, if you know of others in your company or other
companies that should be part of this committee please feel free to
share this with them.

If you have any questions please feel free to let me or those on the
reflector know.

Looking forward to hearing from each of you,

Jon Sanders

P.S. If you were sent this and are not on the Verilog-AMS reflector and
wish to be removed from mailings such as this, please reply back to me
and I will remove you from this list. If you have an alternative from
your company that should be on the list please make sure I have that
information or that they are on the reflector.

***********************************************************
Jonathan L. Sanders
Product Engineering Director
Custom IC Solutions
Cadence Design Systems, Inc.
555 River Oaks Pkwy
San Jose, CA. 95134
 INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408)
944-7027
***********************************************************



This archive was generated by hypermail 2b28 : Mon Feb 24 2003 - 11:06:50 PST