Subject: RE: Minutes of: V-AMS DevModeling meeting July 1
From: Martin O'Leary (oleary@cadence.com)
Date: Mon Jul 07 2003 - 18:13:19 PDT
Geoffrey,
Some comments on strings below and variable initialization below based on the Verilog-AMS committee discussions today.
Thanks,
--Martin
> -----Original Message-----
> 1.8 strings
>
> Strings are allowed in digital context of Verilog-AMS,
> but excluded (AMS-LRM 2.1, section C.2) from Verilog-A.
> Anyone know why they were excluded?
My understanding is that the Verilog-AMS committee never got around to it because it wasn't considered high priority.
> Obviously, it should
> be an error to use the value of a string parameter in
> computing a branch contribution.
>
> We noted that digital "strings" are fixed-length character
> buffers, but model/instance names may be arbitrarily long.
> So, we really want a string, not a "reg" variable.
You can pass an arbitrary length string as a parameter in Verilog - however there aren't operators to find out its length but that is not important for most purposes.
I have attached an example at the end of this email - I tried it on Verilog-XL and it worked fine.
>
> We all agreed that strings should be supported for
> device models.
> 1.9 initialize variables where declared
>
> Sri pointed out that, for a variable declared at top level,
> its domain (digital or analog) is determined by where it
> is assigned a value (digital block or analog block -- can't
> be both). Although the AMS committee wants a better way
> to determine the domain, they haven't found one, so we
> either have to solve this problem or only allow the
> initialization for declarations inside the analog block.
>
We spoke about this in todays Verilog-AMS committee meeting and had the following alternative ideas;
idea 1:
Initializing a variable should make it digital.
If a user wants really wants the variable to be analog, he should prefix it by the keyword 'analog';
e.g.;
analog integer ii = 0;
This is also helpful as a user can force the domain of a variable.
idea 2:
Initializing a variable should not force the domain.
That would depend on subsequent assignments. If the variable is not subsequently assigned, then it should be considered a digital variable.
> David asked if we really need this, or if it's a convenience;
> Marek said his company hadn't needed it in implementing the
> various standard models for his company's simulator.
>
`resetall
`timescale 1ns / 100ps
module top;
MUX2_1 #("ijlknop") mux1();
endmodule
module MUX2_1;
parameter nn = 0;
initial $display("%s",nn);
endmodule
This prints;
"ijlknop"
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