Subject: RE: Minutes of: V-AMS DevModeling meeting July 29
From: Srikanth Chandrasekaran (srikanth.chandrasekaran@motorola.com)
Date: Wed Aug 06 2003 - 00:12:39 PDT
Hi Geoffrey,
The __VAMS_ENABLE__ is part of the LRM2.0 standard that can be implemented
as part of the compiler. That's the only inbuilt `define which is part of
the standard.
cheers,
Sri
The proposal also calls for a token to be `defined by the simulator,
similar to how C compilers pre-define things like -DSUN5 or -DSYSVR4
Cadence also has `ifdef __VAMS_ENABLE__ to distinguish OVI
Verilog-AMS 2.0 from Verilog-A 1.0.
So, we should be able to test
`ifdef CADENCE_SPECTRE
@(above(..))
`endif
because other simulators won't be able to parse the non-standard
above event (until it becomes standard).
Someone asked: do we really need $simulator, if we have `ifdef?
We couldn't come up with a reason; we should be able to do
everything with the `define. We need `define for the non-standard
syntax to be skipped.
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