Subject: VerilogAMS LRM Committee Meeting Minutes - 1st Dec 2003
From: Chandrasekaran Srikanth-A12788 (Srikanth.Chandrasekaran@motorola.com)
Date: Thu Dec 04 2003 - 21:25:18 PST
Date: 1 Dec 2003, 4:30pm PST.
* The changes to the BNF under section A.8.3 and A.8.4 were discussed.
* There were some discussions on the device modelling work thats been happening through the subcommittee.
Reference Document:
BNF Doc: http://www.eda.org/verilog-ams/htmlpages/public-docs/syntax_2_1_updated.pdf <http://www.eda.org/verilog-ams/htmlpages/public-docs/syntax_2_1_updated.pdf>
Please see detailed minutes below.
Discussion on A.8.3 (Expression section)
* Syntax for specifying abstol using nature has been specified for idt and idtmod. This was missing in the previous BNF (only a reference to it was made in section 4)
* Attributes are included as part of the ternary operator. So now the analog_conditional_expression looks similar to the digital counterpart
* BNF for analog_range_expression has been added to the syntax. This is used for referencing particular elements of an digital array - bit select and part select of a digital net. This is specified as analog since solving of the expression itself will happen in the analog solver before the value for the signal is querried from digital.
* analog_expression: Moved most of the syntax from this to a new BNF syntax called analog_primary which is counterpart to the digital primary to be consistent with how digital has specified the language. Refer to "Note" section in the document for that BNF section to get the full details of which syntax have been moved.
* Section A.8 and A.9 from 2.1 BNF (analog expression & expression) has been merged since there was no need to differentiate the same.
* Correction: The first note on this section about "accessibility of genvar primary" is wrong and shall be removed.
* genvar expression is no longer needed. This is merged with the constant expression syntax. Also analysis function is part of constant expression and this will be a semantic restriction to be used in analog only blocks. The constant_expression syntax is common for analog and digital.
* TBD: Number vs Analog Number: AMS syntax supports scale factor extension in number. Do we need to split number to have an analog counterpart or not? This will be discussed further when the section related to that is being discussed.
* With merger of analog and digital constant expressions, paranthesis is allowed as part of constant expression. This isnt currently allowed as per 2.1 BNF.
* Indirect_expressions: These expressions are used for indirect branch contribution statements. Now the syntax has been extended to have abstol for ddt/idt/idtmod operators used in indirect branch contributions.
* Correction: In the BNF being reviewed idtmod is still not being allowed for indirect branch contribution. There is no reason to restrict idtmod syntax in indirect branch contribution. idtmod was not part of original language (1.0) and when later added the BNF was not updated to reflect this in indirect branch usage. This will be corrected and idtmod shall also be allowed in indirect branch contribution statements.
* Correction: In the second syntax for indirect branch expression (idt syntax) the reference should be a port probe. This is cut/paste error in the recent document and will be corrected.
Section A.8.4 (Primaries)
* Analog primary will be same as primary
* Generic identifier has been removed from 2.1 syntax and the new BNF would state explicitly the references - net_ref, var_ref, param_ref
* Moved string into analog_expression from analog_primary to be consistent with digital syntax.
* TBD: Do we need min:typ:max expression in analog_primary??
* constant_primary has been enhanced and added the nature attribute and also the analysis function call as part of this (merge of genvar expression)
* Allowed access of individual element of array parameter which the current 2.1 BNF doesnt support.
General Discussion on collaborating with Device Modeling:
Compact Modelling Doc: http://www.eda.org/verilog-ams/htmlpages/public-docs/Verilog-A_compact_Model_Extensions.pdf <http://www.eda.org/verilog-ams/htmlpages/public-docs/Verilog-A_compact_Model_Extensions.pdf>
* There will be generic discussion on the syntax and individual features of the device modelling extensions thats current being proposed and under discussions as part of the device modeling committee. The AMS committee would like to just take a quick look to make sure that the enhancements and proposals are in conjunction with current work in AMS. This would probably be discussed over one or atmost two calls to make sure there is no conflict with work done in AMS committee.
* First meeting is currently planned to be scheduled for Dec. 15th. These meetings would not go into the details of the proposals as they are already being discussed by experts in the subcommittee, and is purely to see whether there are any potential conflicts with AMS activities.
* The full version of AMS LRM after merger with current 2.1 documentation will go for a final complete technical review if the committee decides to release this as an intermediate version (2.2??) of Accelera before other changes happening in AMS committee.
* The device modeling work extensions, and amendments to the language will be taken up from the base 2.1 version, so that the subcommittee can work from a baselined Accellera approved version. The extensions that are proposed as part of that will be merged into the current changes of AMS BNF by the AMS committee itself.
Next VerilogAMS Committee Call: 8 December 2003, 4:30pm PST.
-- Srikanth Chandrasekaran Global Software Group, EDA Motorola, Australia Ph: +61-8-8168 3592 Fax: 3501
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