Subject: minutes of V-AMS DevModeling Dec 16
From: Geoffrey.Coram (Geoffrey.Coram@analog.com)
Date: Tue Dec 16 2003 - 13:01:32 PST
Attendees:
Geoffrey Coram, Analog Devices
Ilya Yusim, Cadence
Jeroen Paasschens, Philips
John Moore, Agilent
Laurent Lemaitre, Motorola
Jim Barby, U Waterloo
Al Davis, Kettering U
------
1) Approval of previous minutes (Dec 2).
2) Notes from the main AMS call
I'm hoping Srikanth will post minutes from the AMS call,
but here are a few comments:
- I need to provide better justification for why alternate methods
won't work
- many/most of the users of VerilogAMS are digital folks and won't
be happy about implementing our proposals in any case, and
especially if we have too many new keywords, etc.
- units can probably be added to the syntax; descriptions
should be done with attributes
- "aliasparam" would be better than "parameter alias" since alias
might be used in existing modules
- our proposal for output, operating point parameters was rejected,
because digital folks won't want to re-write their modules that
have variables declared at top level; there is apparently some
optimization that can be done now because digital simulators
don't allow probing of module-level variables.
- string variables, variable initialization, and declaring
variables anywhere were all seen as things that are present
in 1364-2001 and/or SystemVerilog. As such, it's easier to
make the case to add them; on the other hand, adding these
piecemeal, as opposed to all at once in a sync'up with one
of these standards, is perhaps not the right approach.
We only got through section 1. The main AMS committee will be
discussing the remaining sections (2-4) on January 5.
3) Discussion of BNF submissions
We discussed the above comments.
No one on the call today was heartbroken about descriptions being
forced into an attribute.
We're OK with aliasparam.
I had a new proposal for output, operating point parameters:
we should allow variables to have a description attribute,
and anything (parameter, variable) with a description should
be an output/op pt parameter. If you bother to type a
description, that should be sufficient indication that the
simulator should print the name,value,description in an
op pt display. One could say
(*description ="" *)
or
(*description ="output parameter" *)
if one doesn't want to be more descriptive. This would not
affect existing modules.
Al thought that we should have some way of specifying a
probe list, perhaps dependent on the analysis. Most of us
felt that a probe list would just be extra typing; the
analysis-dependence would be hard to specify a syntax for,
and it wasn't clear that there are compelling reasons for
wanting to make the list analysis-dependent.
We discussed that $connected and $param_given should be
classified into a new thing and that genvar_expression
should include this new thing for use in an
analog_conditional_statement.
We had some trouble understanding the AMS LRM 2.1, in
particular the distinction between an "conditional_statement"
and a "analog_conditional_statement"; the LRM seems to say
that a conditional_statement can be used in an analog block.
The updated syntax that the main AMS committee is working on
appears to disallow this.
4) Next meeting: January 13, 3 PM Eastern (noon Pacific, 9 PM Europe)
Sri noted that our current 11AM meeting time is 2:30AM in Australia.
We are at a point that his involvement would help our interface with
the main AMS committee, at the expense of inconveniencing our
European contributors. Al Davis also had a conflict in his
winter term schedule. Hopefully, this new time will be OK.
I felt that Dec 30 was probably going to be poorly attended
because of the holidays (shutdowns, vacations, etc.), and I
probably need the extra time to work on the BNF contributions.
-- Geoffrey J. Coram, Ph.D. Senior CAD Engineer Analog Devices, Inc. Geoffrey.Coram@analog.com 804 Woburn St., MS-422, Tel (781) 937-1924 Wilmington, MA 01887 Fax (781) 937-1014
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