Subject: RE: V-AMS DevModeling Feb 10
From: Peter Liebmann (peterl@xpedion.com)
Date: Tue Feb 10 2004 - 11:35:54 PST
I would like to comment on limiting in Verilog_a.
It has been proposed that limexp is sufficient for device. I do not
believe
this.
Consider, for example, a diode:
Is*(exp(v/vt)-1)
Limexp can either have the exponent go linear after a certain point, or
perform a more complicated, SPICE type algorithm which uses information
about
previous values of v/vt which depends on the simulation cycle for an
iteritive type simulator.
If a simulator goes linear for a value of v/vt greater than some
tolerences,
the desired solution may change if the tolerance is too small. This is
similar to the use of Imelt in some simulators.
Imelt is the point where a diode goes linear. limexp, however, does
not take into account The Is of the diode which is necessary for imelt
to work properly.
One can write there own diode model for Imelt in verilog_a:
if(v/vt > tol)
a=Is*(exp(v0/vt)+...); // linerized - v0 a function of Is
else
a=Is*(exp(v/vt)-1);
However, this will change answers if Imelt is not desired.
The only solution I can think of is allowing SPICE type of limiting.
To do this, we need the following:
1. Only allow limiting on branch voltages.
2. Provide the following routines:
a. last_value(V(n1,n2)) - provide the last iteration of the branch
voltage
b. limit(V(n1,n2),vnew) - tell the simulator what the new branch
voltage is.
c. save(var,var_save) - save a variable "var" in some other variable
"var_save"
The semantics of these routines will be dependent on the simulator.
For example, last_value would only return Newton-Raphson iteration
values
dependening on where one is in a simulation cycle.
Limiting may not always be preformed - again depending on the simulation
cycle.
If limiting occures, the limit routine can reject that Newton Raphson
iteration.
Save is necessary for fetlim type of limiting.
In conclusion, I feel that these 3 routines are all one needs to do
SPICE type
limiting (I can write more details later - but I wanted to get these
ideas out
now).
As an example, limit V(n1,n2) not to be > last_value +5;
last_v = last_value(V(n1,n2));
if(V(n1,n2)>last_v+5)
limit(V(n1,n2),last_v+5);
It is importent to note that it is up to the simulator to figure
out when to limit and what last_v to provide!! The user need not be
Concerned with the simulation cycle.
------------------------------------------------------------------------
S. Peter Liebmann, Ph.D.
Xpedion Design Systems, Inc.
Tel: 408-449-4024
E-Mail: peterl@xpedion.com
-----Original Message-----
From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Geoffrey.Coram
Sent: Monday, February 09, 2004 1:10 PM
To: Verilog-AMS LRM Reflector
Subject: V-AMS DevModeling Feb 10
Good grief. My apologies: the last e-mail had dates for
the meeting, neither of which was correct. (The hazards
of editing an old message to keep the call-in info.)
The date is February 10.
Greetings -
The device modeling extensions subcommittee will be meeting Tuesday,
February 10, at 3 PM Eastern (noon Pacific, 9 PM Europe).
The dial-in information is below; thanks again to Ilya
and Cadence for sponsoring it.
> Toll-Free Number: 888-454-9810
> Toll Number: 1-415-228-4715
>
> PASSCODE: 92821
We'll continue our discussion of limiting, and hopefully
cover some of the paramset proposal.
-Geoffrey
-- Geoffrey J. Coram, Ph.D. Senior CAD Engineer Analog Devices, Inc. Geoffrey.Coram@analog.com 804 Woburn St., MS-422, Tel (781) 937-1924 Wilmington, MA 01887 Fax (781) 937-1014
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