Subject: RE: Minutes of LRM committee Meeting
From: Vassilios.Gerousis@Infineon.com
Date: Wed Feb 25 2004 - 21:44:51 PST
Hi Sri,
As we discussed, before, that the next version of Verilog-AMS will
become essentially SystemVerilog-AMS. The Accellera Board approved this
move. We will complete SV effort by April/May, and then we both be ready to
work on SystemVerilog-AMS. Your focus now, as we discussed is to continue
LRM cleanup. By April/May, we will start jointly and with appropriate
resources to work on Version 3.0 of the AMS which will be compatible with
Accellera 3.1A release. We also need to examine the simulation semantics and
how we can fit the two together. Resources will be applied in April/May to
kick-off this activity.
Kevin is ahead of many your team, and he understand SV. It will be
good for the rest of the team to educate themselves on SV.
We will talk more as the time get closer.
Vassilios
-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf
Of Chandrasekaran Srikanth-A12788
Sent: Thursday, February 26, 2004 6:15 AM
To: 'Kevin.Cameron@nsc.com'; 'verilog-ams@eda.org'
Cc: 'Vassilios.Gerousis@infineon.com'
Subject: RE: Minutes of LRM committee Meeting
Hi Kev,
I agee with some of your comments. But at the same time currently we have an
AMS LRM which is being used quite widely by both implementors and designers
who are using this language. The language has loop holes, and issues that
need to be sorted out and refers to IEEE 1995 which is an obsolete language
at this point of time. Now there are two choices - merge with 2001/2005 or
with SV3.1.
Since the whole VerilogA language was naturally derived from 1995 (ofcourse
I wonder sometimes why we deviated from it in so many places), merging with
2001 was a short term task which atleast makes the LRM current in terms of
all its references and removes lot of ambiguities in terms of syntax and
semantics in the language. So part of the task was to make the language have
a good implementation grammer and have the same interpretation for people
reading it, designing with it and wanting to implement it.
Now coming to making AMS language into IEEE - I see the language as a
subsection to either the 1364 standard or SV standard. From what I
understand Accellera has a clear directive on merging SV with AMS. But this
effort is more involved as there is a reasonable effort that needs to go
into rewriting the mixedsignal portion. I am okay to donate AMS to the SV
committee and we can still operate the current committee under the new home
and work on the analog/mixed signal enhancements required for users to use
it. Then the problem of language merger is not fully owned by the current
"Verilog"AMS committee. Ofcourse there are different stakeholders on this
and there are differing opinions - as you pointed out VerilogAMS currently
has more participation from cadence where as SV is mainly controlled by
Synopsys.
cheers,
Sri
> -----Original Message-----
> From: Kevin.Cameron@nsc.com [mailto:Kevin.Cameron@nsc.com]
> Sent: Thursday, February 26, 2004 1:35 PM
> To: verilog-ams@eda.org
> Cc: Chandrasekaran Srikanth-A12788; Vassilios.Gerousis@infineon.com
> Subject: RE: Minutes of LRM committee Meeting
>
>
>
> > Hi Kev,
> >
> > I was in discussion with Vassilios sometime ago about this
> point and I think the approach for this would be for some of
> the SV committee volunteers to participate in AMS to merge
> the two language together. Currently I don't think we have
> the bandwidth or the appropriate volunteers in the AMS
> committee to achieve this task. I have raised this as an
> issue at the Accellera Board Meetings.
> >
> > I know that this is high priority for both SV and AMS
> committee as well as the Accellera Board to get an SV-AMS and
> take it to the IEEE as a standard, but unfortunately unless I
> get SV experts participating it is difficult to make it
> happen, which can happen parallely with all the other
> activities that I have outlined in my very short term plans
> in the mail.
> >
> > cheers,
> > Sri
>
> I don't think it's particularly high priority for the SV team
> - SV has been driven
> mostly by Synopsys effort, and Synopsys hasn't been a big
> participant in Verilog-AMS
> over the years (AMS is mostly driven by Cadence on the vendor side).
>
> Spending a lot of time polishing the AMS BNF isn't much use
> if it is going to be
> rewritten by the other committees anyway, so there's no real
> reason for not donating
> the AMS LRM to the other committees ASAP.
>
> I'll be happy to work on integrating the languages when I get
> the opportunity, but
> there doesn't appear to be a committee focusing on that
> problem at present, and I
> don't think there will be until the LRM is handed off.
>
> Kev.
>
>
> >
> > > -----Original Message-----
> > > From: owner-verilog-ams@eda.org
> > > [mailto:owner-verilog-ams@eda.org] On Behalf Of Kevin Cameron
> > > Sent: Thursday, February 26, 2004 5:22 AM
> > > To: verilog-ams@eda.org
> > > Subject: RE: Minutes of LRM committee Meeting
> > >
> > >
> > >
> > > Chandrasekaran Srikanth-A12788 wrote:
> > >
> > > >
> > > > This was a very brief meeting just to discuss the plans and the
> > > various proposals that are planned to be discussed in the
> near future.
> > > >
> > > > * Currently we have updated the grammer to have the digital
> > > and analog
> > > syntax in sync and we need to propogate these changes to
> the actual
> > > sections and update the syntax snippets specified in the
> chapters and
> > > also clarify the semantics that was identified during the review.
> > > > * Updating the sections is fairly long process and this
> > > will happen in
> > > a parallel thread while reviewing some of the other proposals
> > > that need
> > > to be discussed and updated in the LRM.
> > > >
> > > > * Some of the outstanding proposals that will be discussed
> > > in the next
> > > couple of months are:
> > > > - $table_model (will be discussed on 8th March)
> > > > - DC Sweep specification in LRM (will be discussed on
> 22nd March)
> > > > - IC Analysis (will be discussed on 5th April)
> > > > - m-factors syntax in behaviour (this is currently
> being discussed
> > > in device modeling committee also)
> > > > * The BNF updates will be a parallel process and will be
> > > reviewed once
> > > the above feature proposals have been reviewed.
> > > >
> > > > * The above proposals will hopefully be available a
> week in advance
> > >
> > >
> > > I would just like to note that the work currently going
> on does not
> > > appear to be leading towards an IEEE Verilog-AMS standard. The
> > > SystemVerilog committees appear to be working on a tight schedule
> > > to clean up their LRM for submission to the IEEE and are not
> spending any time
> > > considering integrating Verilog-AMS. If SV gets to the IEEE
> > > much ahead of
> > > AMS, integration will be much harder, and could be pushed off
> > > indefinitely.
> > >
> > > The plan this time last year was just to clean up the BNF
> and minor
> > > issues and submit the LRM to the IEEE and/or to roll it into
> > > SystemVerilog
> > > before the end of 2003.
> > >
> > > Is there any date for that happening now?
> > >
> > > Kev.
> > >
> > > > cheers,
> > > > Sri
> > > > --
> > > > Srikanth Chandrasekaran
> > > > Global Software Group, EDA
> > > > Motorola, Australia
> > > > Ph: +61-8-8168 3592 Fax: 3501
> > > >
> > >
> > >
> > > --
> > > Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862
> > >
> >
>
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