Subject: RE: Minutes of LRM committee Meeting
From: Chandrasekaran Srikanth-A12788 (Srikanth.Chandrasekaran@motorola.com)
Date: Wed Feb 25 2004 - 15:55:40 PST
Hi Kev,
I was in discussion with Vassilios sometime ago about this point and I think the approach for this would be for some of the SV committee volunteers to participate in AMS to merge the two language together. Currently I don't think we have the bandwidth or the appropriate volunteers in the AMS committee to achieve this task. I have raised this as an issue at the Accellera Board Meetings.
I know that this is high priority for both SV and AMS committee as well as the Accellera Board to get an SV-AMS and take it to the IEEE as a standard, but unfortunately unless I get SV experts participating it is difficult to make it happen, which can happen parallely with all the other activities that I have outlined in my very short term plans in the mail.
cheers,
Sri
> -----Original Message-----
> From: owner-verilog-ams@eda.org
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Kevin Cameron
> Sent: Thursday, February 26, 2004 5:22 AM
> To: verilog-ams@eda.org
> Subject: RE: Minutes of LRM committee Meeting
>
>
>
> Chandrasekaran Srikanth-A12788 wrote:
>
> >
> > This was a very brief meeting just to discuss the plans and the
> various proposals that are planned to be discussed in the near future.
> >
> > * Currently we have updated the grammer to have the digital
> and analog
> syntax in sync and we need to propogate these changes to the actual
> sections and update the syntax snippets specified in the chapters and
> also clarify the semantics that was identified during the review.
> > * Updating the sections is fairly long process and this
> will happen in
> a parallel thread while reviewing some of the other proposals
> that need
> to be discussed and updated in the LRM.
> >
> > * Some of the outstanding proposals that will be discussed
> in the next
> couple of months are:
> > - $table_model (will be discussed on 8th March)
> > - DC Sweep specification in LRM (will be discussed on 22nd March)
> > - IC Analysis (will be discussed on 5th April)
> > - m-factors syntax in behaviour (this is currently being discussed
> in device modeling committee also)
> > * The BNF updates will be a parallel process and will be
> reviewed once
> the above feature proposals have been reviewed.
> >
> > * The above proposals will hopefully be available a week in advance
>
>
> I would just like to note that the work currently going on does not
> appear to be leading towards an IEEE Verilog-AMS standard. The
> SystemVerilog committees appear to be working on a tight
> schedule to clean
> up their LRM for submission to the IEEE and are not spending any time
> considering integrating Verilog-AMS. If SV gets to the IEEE
> much ahead of
> AMS, integration will be much harder, and could be pushed off
> indefinitely.
>
> The plan this time last year was just to clean up the BNF and minor
> issues and submit the LRM to the IEEE and/or to roll it into
> SystemVerilog
> before the end of 2003.
>
> Is there any date for that happening now?
>
> Kev.
>
> > cheers,
> > Sri
> > --
> > Srikanth Chandrasekaran
> > Global Software Group, EDA
> > Motorola, Australia
> > Ph: +61-8-8168 3592 Fax: 3501
> >
>
>
> --
> Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862
>
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