minutes of: V-AMS DevModeling meeting March 23

V-AMS Compact Modeling Extensions subcommittee
Minutes of Mar. 23, 2004

Attendees:
Geoffrey Coram, Analog Devices
Ilya Yusim, Cadence
Marek Mierzwinski, Tiburon
Patrick O'Halloran, Tiburon
Jim Barby, U Waterloo
Adam Divergilio, Tektronix
Ernest McReynolds, Tektronix

1) Approval of previous minutes (Feb 24)

2) CMC meeting and NanoTech2004

Several presenters at the NanoTech2004 "Workshop on Compact Modeling"
talked about Verilog-A. Jane Xi from Berkeley said they had tried
the next-generation BSIM in Verilog-A, but had simulator problems.
Michael Schroter had simulator problems with his Verilog-A version of
HiCUM.

Shiuh-Wuu Lee from Intel said he needs to do robust porting of
standard models for its requirements, but protect Intel's IP.

At the Compact Model Council meeting, Ivan Pesic of Silvaco talked
about allowing parameters in Spice .model cards to be functions of
L and W.

Someone from Infineon needed to change the gate resistance calculation
for BSIM4; some parameters needed to be instance rather than model
parameters.

These last items would be solved by Verilog-A.

There was also a suggestion that candidates for the next-generation
MOSFET model be required to have a Verilog-A implementation for a later
phase, when all CMC members will be evaluating the model. This
requirement was softened by accepting implementation in a "commercial
simulator," though Verilog-A is likely the much easier route, unless
the model is already in a commercial simulator (Penn State's SP model
will likely be a contender, and Motorola is working to implement it in
Spectre).

My presentation at the Compact Model Council meeting was well received.
People were impressed that Verilog-A had allowed me to implemented
self-heating in BSIM3 in about 10 lines and about 2 days (Berkeley has
been asked to investigate implement self-heating in BSIM3 and BSIM4 for
LDMOS modeling).

People were concerned about the simulator implementations:
- which ones have compiled interfaces?
- how will we know which extensions have been implemented?
So the CMC chairman will ask the EDA vendors periodically to provide
a status report on the Verilog-A implementations.

Colin's prototype resistor model was distributed in Verilog-A.

3) Limiting

I've been trying to make the case for limiting by running the
CircuitSim93 test cases using Verilog-A models. I had my own
BJT model (for our enhanced GP), and Silvaco posted a MOS level 3
model on the web.

I'm running all of these in ADI's internal simulator. Note that
I only tested the time=0 / dc solution, not the transient or dc sweep.

For the BJT circuits:
5 succeeded in DC Newton with built-in models, but required a
   homotopy with Verilog-A models
4 succeeded in DC Newton with either model type
3 needed a homotopy with either model type
1 (ring11) uses mos level2 in addition to bjt

For the MOS level 3 circuits:
10 succeeded in DC Newton with built-in models, but required a
   homotopy with Verilog-A models
3 succeeded in DC Newton with either model type (and all
   were such that the initial guess was the solution -- all
   voltages were zero unless driven by a voltage-source)
1 needed a homotopy with the built-in models

The MOS level 3 circuits seem to make a compelling case for the need
for limiting. I still need to show that our proposed syntax gives us
everything we need. It may be that we need additional syntax to
give the initial guess. For example, in the BJT, the B-E junction
is usually limited with pnjlim, and the initial guess is the same
Vcrit that is used by pnjlim; however, the B-C junction is
initialized to 0 instead of Vcrit. So, we might need
   Vbe = $limit(V(b,c), "pnjlim", Vcrit, Vcrit);
   Vbc = $limit(V(b,c), "pnjlim", Vcrit, 0.0);
The original idea was that the limiting function would be called
with V(b,c), the previous value of V(b,c), and then the third
and any subsequent arguments to $limit would be passed as the
third and subsequent arguments to the limiting function. Will
limiting functions always only have one argument? Should we
specify the initial guess in some other manner?
   Vbc = $limit(V(b,c), "pnjlim", Vcrit) (*initial_guess=0.0*);

Ilya asked: what if limiting is not written by the model developer?
Spectre still needs to converge. Will the model developers accept
our proposed extensions and make use of them?

I believe they will, insofar as they are accustomed to putting
the calls in their C code (eg, Berkeley's BSIM3/4).

I mentioned that I don't have a MOS level 2 Verilog-A model to
try the remaining CktSim examples. Tektronix offered to try to
convert their level 2 model in their proprietary modeling language
into Verilog-A for this effort.

Ilya said that Cadence has updated the CktSim circuits to use BSIM3
models by simply using model cards from a standard TSMC process.
He will check if he can release these updated circuits.

Jim noted that some model parameters in original CktSim chosen to
cause problems in some circuits, so using real model cards will miss
these pathologies.

Ilya ran Cadence's regression tests without "region" parameter
(which provides an initial guess for Newton) and did not see
any/many convergence problems -- but then, the regression
suite is not designed to test convergence. He will try the
CktSim examples.

4) Next meeting: April 6, 3PM Eastern.

-- 
Geoffrey J. Coram, Ph.D.    Senior CAD Engineer     
Analog Devices, Inc.        Geoffrey.Coram@analog.com 
804 Woburn St., MS-422,     Tel (781) 937-1924
Wilmington, MA 01887        Fax (781) 937-1014