RE: V-AMS DevModeling meeting April 6, new proposal doc

I was having a look at the proposals and it occurs to me
that more stuff is being invented than is necessary.

Since the long term aim is to combine Verilog-AMS and
SystemVerilog, solutions should be taken from the SV LRM
if possible. E.g. (SV LRM 10.5.2 Pass by reference) obviates
section 3.1 (More flexible functions), and 4.1 (Optional ports)
is probably covered by interface modports (SV LRM 19.4).

Paramsets could probably be implemented on top of SV classes,
and binning can probably be handled with "generate".

http://www.eda.org/sv-ec/SystemVerilog_3.1_final.pdf

BTW, an issue I tried addressing in the early days of Verilog-A
was the use of multiple gate/source/drain or base/emitter/collector
devices, after a designer friend told me that many design failures
were due to people dumping devices into the same well and not getting
the same results on Silicon as the simulator since the netlist didn't
carry that information and the devices look independent. If anyone
has suggestions for solving that problem I'm sure the users will
appreciate it.

Kev.

Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862
Received on Fri Apr 2 15:24:33 2004