Re: V-AMS DevModeling meeting April 6, new proposal doc

Geoffrey.Coram wrote:

>What I meant was that model cards are set up outside
>of the model equations (not independent).
>
>With paramsets, one would have a single module
>definition, say for BSIM5, and then several paramsets
>would set parameter values for the module.
>
>If one tried to use generate statements, you'd have
>to repeat the module definition each time to put
>different parameters in for the different devices
>(core, i/o, low-vt, medium-vt, whatever).
>
>-Geoffrey
>
I was suggesting generate statements for binning because only the internal
behavior of the model changes, the ports don't . You can do
sub-(macro)module
instantiation to call a single definition with different parameter
overrides if you
want to do it that way.

You could also use Verilog 200X configurations (LRM 13.3.1.6 The use
clause).

Either way I don't think you really need to add a new construct for
parameter sets
or binning. In general it will be easier to add extra functionality to
either of the existing
mechanisms than to invent a new one.

Similarly, "aliasparam" is probably unnecessary if you can say "ref
param" (which
isn't allowed at the moment), or re-use the alias statement (currently
only for signals).

Kev.

>
>
>
>"Geoffrey.Coram" wrote:
>
>
>>Kevin -
>>I found more detail about generate in 1364-2005-d2.pdf
>>(http://www.boyd.com/1364/1364-2005-d2.pdf.gz)
>>
>>and it doesn't work at all for paramsets. Generate
>>statements must lie within a module, but paramsets
>>(and their spice "equivalent", .model cards) are
>>set up independent of the module.
>>
>>The way paramsets are proposed, one might even choose
>>to have a particular instance simulated by one of two
>>different modules.
>>
>>-Geoffrey
>>
>>

-- 
Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862