Minutes of the AMS committee Meeting - 19 April 2004

Attendees: Geoffrey Coram (Analog Devices), Martin O'leary, Jon Sanders (Cadence), Sri Chandra (Motorola), Jim Barby (U Waterloo)
Date: 19 April 2004, 4:30pm Pacific time

The main proposal that was discussed with the DCSweep proposal.

The following comments were made on the proposal:
* It was commented that analysis("nodeset") will return TRUE only while performing nodeset - only during the nodeset phase of the dc iteration. Its not necessary that DC operating points will always have a nodeset phase - and when there is no nodeset being performed the return value of this function will return FALSE.
* If a model writer wants to trigger a particular statement just for the first dc point and not for the subsequent points initial_step("dc") should be used rather than using analysis("nodeset") as this is not guaranteed that nodeset phase will always be there during a dcpoint.
* Preferable to have the points called d1, d2, ... dN instead of dc1,dc2 etc and also rename the column heading to say DCSweep instead of Sweep. Also was pointed that its better to refer to "dc" in lowercase rather than uppercase to be consistent with the IEEE format in the documentation.
* There was some confusion regarding "rotation" of variables and what it means - it was decided to drop the first sentence in the second paragraph in "DC Analysis" section. The subsequent sentence anyway states - "The values of the variables in the previous dc point will be used as the starting values for the next dc point".
* there is a mistake for final_step("unknown") which should return 0 instead of 1.

* The current proposal does not clarify what the behaviour of dc sweep should be for a mixed signal design. Its clear in terms of analog-only but should also clarify how the digital solvers should behave - this is related to the same issue as resolving operating point values for mixed signal (including initial condition values done to find the operating point for a transient analysis). Part of this problem would be resolved by the IC analysis proposal also that might be discussed very soon.
There were couple of suggestions in terms of dealing with dc sweep (and also probably ac analysis) wrto mixed signal
* One of the suggestions was to state that dc sweep analysis is done on the analog portion of the circuit and will use the digital values/states at that point of time.
* Discussions regarding triggering of mixed signal events (cross in digital) during a sweep analysis. Its quite likely that the digital solvers need to be solved and be able to handle mixed signal events. During a dc sweep its quite likely that the voltage may cross a threshold that might change the state in digital block and triggering a d2a event. So events need to be handled in this case. If there is feedback this might trigger an analog to digital event also while finding the dc operating point. Not having to handle mixed signal events during IC analysis of a transient simulation might be okay in most cases but seems like it will be more critical to handle it during voltage sweep analysis.
* Verimix: Currently in verimix cadence mentioned that during the operating point step they run the digital solver in transient time until there are no further mixed signal triggers/events. Once that state is reached that time in digital is stamped as time 0.
* Another suggestion was to execute the digital solver with 0 delay until there are no pending digital events at current time (rather than no pending digital events at all??)

* Geoffrey asked whether dc sweep will need to be put in the compact modeling extensions. It was felt that having it in the main AMS LRM is probably an more appropriate place since it handles both pure verilog-a designs as well as handling mixed signal. The issue is will the mixed signal issues for dc sweep be resolved in time for compact modeling extension are to be approved?
* For LRM2.2 the current plan is to include the compact modeling proposals that have been agreed upon and also all the proposal that have been discussed as part of the main committee - table_model, dcsweep, etc. Hopefully in the coming weeks the mixed signal issues for DC point will also be resolved. Otherwise one way of addressing it is to make sure dc sweep behaviour is properly reflected for analog (so that compact modeling can make use of it) and address mixed signal issues parallely into a next revision.

The following items will be discussed in the next AMS committee call:
* mfactor and its impact with regards to verilogAMS hierarchical instantiations and how these scaling factors are going to be passed through.
* Discussion on how digital solvers, mixed signal behaviour should be handled for dc sweep and other operating point analysis.

* Geoffrey also requested that the next revision of compact model extensions be reviewed in the main AMS committee. This is scheduled for end May before the proposal gets presented to the Accellera board during DAC. The actual techincal board review and formal approval process for LRM2.2 is planned post DAC around June-July timeframe.

Regards,
Sri

--
Srikanth Chandrasekaran
Global Software Group, EDA
Motorola, Australia
Ph: +61-8-8168 3592 Fax: 3501