Name-Clash solution proposal

A possible solution to the type name problem is to add some extra
functionality to SystemVerilog (it will only be one of many fixes), namely:

    untypedef <name>

If the existing (clashing) types are reimplemented as predefined
typedefs then they can be undefined when old code is encountered e.g.:

    typedef _sv_type_logic logic; // pre-defined at start-up

    untypedef logic; // forget "logic"
    `include "old_code.vams"
    untypedef logic; // in case it got typedef'd again
    typedef _sv_type_logic logic; // reinstate old definition

This should be relatively easy to implement since the type scheme in SV
is handled dynamically and this change wouldn't break any existing SV
code. You could temporarily limit the functionality to only allow the
redefinition to be the same as the first definition (which makes it even
easier to implement), but I think in the long term a mechanism is
required that allows local redefinition of types anyway.

Note 1: typedef'd types should take precedence over AMS types

Note 2: "logic" would not be a keyword so it can be used in the same way
that it was before in AMS.

Note 3: You could put all the SV basic types in a standard header file
as typedefs of built-ins with long (unlikely to clash) names.

Note 4: I'm sure you can unilaterly implement functionality you need in
SV and donate it to Accellera - other folk will be facing the same
problem (eventually).

I may have proposed this before at the SV committee - but I can't find a
reference.

Kev.
Received on Mon May 3 18:08:07 2004