descriptions as attribute

The main AMS committee suggested that parameter descriptions
be assigned through an attribute, specifically a standardized
attribute, which I thought would look like this:
  parameter real res = 1 from (0:inf) (*desc="resistance"*);

However, when I look at SystemVerilog 3.1 or 1364-2005, the
attribute_instance for a parameter declaration *precedes*
the declaration, eg
  (*desc="resistance"*) parameter real res = 1 from (0:inf);

This would make for ugly code; lining up "parameter real" for
the 600 parameters of BSIM4 would take a lot of padding.

Any comments?

-Geoffrey

PS: my previous post about VHDL-AMS using -- for descriptions
was wrong; the double-dash is a comment in VHDL, and thus the
text after it is not associated with the parameter like we
want the description to be.
Received on Tue May 11 10:05:34 2004