RE: net discipline declaration

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Geoffrey.Coram
> Sent: Wednesday, May 12, 2004 6:46 AM
>
> The new syntax (syntax_2_1_updated.pdf) has the same problem
> of allowing "electrical [0:1] n1 [0:3];"
>
>
> net_declaration ::=
> ...
> | discipline_identifier [ range ] list_of_net_identifiers ;
> | discipline_identifier [ range ] list_of_net_decl_assignments ;
>
>
> list_of_net_decl_assignments ::= net_decl_assignment { ,
net_decl_assignment }
> list_of_net_identifiers ::= net_identifier [ dimension { dimension }]
> { , net_identifier [ dimension { dimension }] }
>
> net_decl_assignment ::= net_identifier = expression
>
>
> The update does take care of allowing nodesets for scalar nodes, but
> apparently not for arrays.
>
> Kevin Cameron wrote:
> > the prefixed range is the bit-width for Verilog e.g. a 16-bit
> > integer could be -
> >
> > reg [0:15] i16;
> >
> > an array of them is
> >
> > reg [0:15] a16[0:7];
> >
> > So both "reg [0:4] w" and "reg w[0:4]" create 5 wires, but
> > In the first case "w" is an integer type and the second "w" is an
> > array.
>
> However, the examples in the AMS LRM seem to use the prefixed
> range for the array. For example, in section 3.4.3.1 on page 3-16,
> electrical [0:4] bus = {2.3,4.5,,6.0}; (*)
>
> I was hoping that the array was the postfixed range, in which case
> there was a simple tweak to the syntax to show that an array of
> nodeset values was only allowed for an array of nodes. The
> syntax gets too long for one line when I add the description
> attribute.
>
> Based on Kevin's message, the example (*) does not make sense;
> the nodeset value should be a 5-bit integer, not an array.
>
> -Geoffrey

It may make sense if the bus is also declared as a port connected
(to something digital) as wire [0:4] bus. I think you can infer from
the "electrical" context that it's an analog assignment (much as if
it appeared in an analog block). So while it's a bit inconsistent I
don't see it as a major problem.

Kev.

Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862

>
>
> Chandrasekaran Srikanth-A12788 wrote:
> >
> > Hi Geoffrey,
> >
> > I raised this issue a while ago (3 years ago) - what does it mean to
have a range before and after
> a net identifier. This was introduced in 2.0 (I think). At that time
the explanation given was - it
> was done to make the BNF consistent between analog and digital and
doesn't mean anything in the
> analog context and should never have a analog declaration like that in
the analog context. It was
> basically added to suppor the "memories" syntax of the digital world.
(Still I don't understand why
> it was put in the analog BNF - unless I didn't get a complete
explanation of the addition.)
> >
> > Graham reworked on the BNF recently to merge digital and analog -
removing the ambiguities and
> merging some of the syntax (and identifying the semantic restrictions
of the same in the analog
> context). I am not sure whether this problem exists in the new syntax
that he did just a while ago.
> This new revised draft syntax can be accessed from the VerilogAMS
webpage.
> >
> > Ofcourse for the device modelling extension you will be doing your
changes on 2.1 but these issues
> hopefully will get corrected once we integrate the new syntax.
> >
> > Regards,
> > Sri
Received on Wed May 12 10:12:32 2004