RE: Minutes of: VAMS Compact Modeling conf call May 20

And how does this compare with the string data type in SystemVerilog?

Regards
David

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
Sent: Thursday, May 20, 2004 9:37 AM
To: Martin O'Leary
Cc: VerilogA Device Modeling Reflector; verilog-ams@eda.org
Subject: Re: Minutes of: VAMS Compact Modeling conf call May 20

Martin -
The string parameter as proposed does have its type defined
in the declaration statement.

If I have a string parameter like

  parameter string type = "nmos" from {"nmos", "pmos"};

then I am saying that the simulator should allocate a 4-character
string (plus \0 ?) for that parameter; any string that is longer
than 4 characters must be considered as outside the allowed range
and thus the simulator does not have to keep track of it.

-Geoffrey

Martin O'Leary wrote:
> > 4. String parameters
> >
> > Sri asked if the range (from {"a", "b"}) is mandatory.
> > This tells the simulator how much space to allocate for the string,
> > (similar to how digital reg variables have a size), so I believe
> > it should be mandatory.

> Could someone elaborate more on this point? If the point is that the module should indicate the maximum number of chars the string
should have - this is not correct. In Verilog, parameter sizes and indeed types are not finally determined until elaboration time.
Received on Thu May 20 09:51:08 2004