Kevin Cameron wrote:
> I view it as implementation specific. In particular I would probably
> translate spice to Verilog-AMS such that the n/p choice was in the
> module name and not a parameter at all, and there's no reason why the
> flag has to be -1.
In compact models, the equations for N and P devices are exactly the
same, except for the -1 factor. Spice "knows" about devices named
"nmos" and "pmos" but the equations are only written once. And
the flag is *always* -1 because that's the right way to convert
the equations.
> Your using parameters the same way Spice does. There's no particular
> reason a device modeler would use a model parameter for that purpose in
> Verilog-AMS - I think it's a particularly bad idea myself.
A device modeler certainly would use a parameter for that purpose,
rather than maintaining two copies of the module code.
> NB: Verilog
> has different primitives for n & p transistors as (nmos, pmos), so you
> can't do plug & play between analog and digital very easily if you move
> the differentiation to a parameter.
Well, the parameter doesn't have to be explicit. If you used paramsets,
you could have
paramset nmos bsim3v3
localparam string type="NMOS";
...
endparamset
paramset pmos bsim3v3
localparam string type="PMOS";
...
endparamset
> >Verilog *requires* a default value for all parameters; however,
>
> That's probably legacy from before there were ranges.
Ranges still aren't part of SV, as near as I can make out
in the 3.1a LRM. When were they added to 1364 Verilog?
They were certainly not in 1364-1995, since V-AMS
notes their addition to that spec; they are present in
the 1364-2005 draft. But I guess they're not in 1364-2001
or else they would have made it into SV already.
So, I think it would be a big battle to advocate removal of
the default.
-Geoffrey
Received on Thu May 20 12:41:07 2004
This archive was generated by hypermail 2.1.8 : Thu May 20 2004 - 12:41:13 PDT