----- Begin Included Message -----
From: Steven Sharp <sharp@cadence.com>
Kevin Cameron wrote:
>It don't see why the BTF would be considering this, it is a purelyanalog
>extension, and Verilog-A has not been donated to the IEEE or integrated
>with SystemVerilog. The simulation semantics of [System]Verilog are such
>that m-factor is meaningless in a digital context, it would only be useful
>to indicate scaling to backend tools (for which you could just use an
>attribute or parameter).
>From what I understand about mfactors, I agree with Kevin. I see no
>purpose for m-factors in digital Verilog.
Geoffrey Coram wrote:
> I don't know, from a digital
> perspective, if a "mfactor=2" inverter should mean that
> the digital block should have twice the drive strength
> (I assume that digital tools do check the fanout of gates).
Digital Verilog does not concern itself with drive strength in this
quantitative way. Fanout and loading are not modeled or checked in
the language. There are backend tools that will check design rules
and back-annotate delays based on factors like loading. They need
extra non-Verilog information about the device characteristics to
do this.
Verilog just isn't intended to model at this level.
Steven Sharp
sharp@cadence.com
----- End Included Message -----
Received on Thu May 27 01:48:28 2004
This archive was generated by hypermail 2.1.8 : Thu May 27 2004 - 01:48:36 PDT