Re: VAMS-CM: new LRM draft, DAC meeting

Geoffrey.Coram wrote:

>Kevin Cameron wrote:
>
>
>>I'd rather extend the [macro]module syntax/semantics to support what you
>>need than add a whole new construct, e.g. add inheritance to [macro]modules
>>so that you don't have to redefine stuff:
>>
>> module mos (...)
>> ...
>> endmodule
>> macromodule my_mos interface mos; // inherit port and parameters etc. from mos
>> ...
>> mos #(...) (.*);
>> endmodule
>>
>>I suggest "interface" rather than "extends" (or ":") since you don't want to
>>inherit the internal structure and processes (and "interface" is already a
>>keyword).
>>
>>
>
>(Interface is a keyword in SV3.0 and later, but not in 1364-2001 nor AMS.)
>
>It's an interesting suggestion. A few points:
>
>1) We don't want to inherit parameters from mos, only the ports
>(and output variables).
>
You could override them locally or maybe disinherit(?) them, but I think
it would be useful to be able to inherit them since they are part of the
interface. I was thinking that you would probably want to do something like:
 
   macromodule n_spice interface nmos; // base n_spice on digital primitive
      parameter real l,w; // add length,width
   endmodule
   macromodule my_n_tran interface n_spice; // inherit l/w from n_spice
      parameter my_parm1; // add some more parameter
   endmodule

>2) It's not clear to me that this is really what the SV interface
>is meant to do.
>
>
It isn't, but it seems like reasonable reuse of the keyword to me.

>3) It seems that the interface, that is, the base module definition,
>would need to preceed the macromodule my_mos; but in typical use,
>I doubt the bsim6 module definition would even be in the same file
>as the paramsets/macromodules.
>
>
That's what header files are for - I don't think it would be much of a
problem. BTW, Verilog doesn't have file scope.

Kev.

>-Geoffrey
>
>
Received on Thu Jun 17 12:51:18 2004