Re: VAMS-CM: new LRM draft, DAC meeting

Kevin -

Kevin Cameron wrote:
> Surely you would only disinherit the 2 (l & w) if the rest are shared? - you only need
> to remember the overrides on the inheritance path.

I think you're not quite following the concept. Think model card
in Spice. (I also have a lot of work to do on putting examples
in the LRM draft.)

Suppose I have the following:

  module bsim6 (d,g,s,b);
      inout electrical d,g,s,b;
      parameter l, w, vth0, tox, vfb, kp, nsub, ... // 600 of these
      (*desc = "transconductance"*) real gm;
      (*desc = "gate-source capacitance"*) real cgs;
      ...
  endmodule

Now, I want to set up a way to access this module in such a way
that the paramset/macromodule sets the values of the "process
specific" parameters vth0, tox, etc., and the user can only
specify l and w. Also, I want gm and cgs to be available.

I will have

  paramset nch bsim6; // standard nmos
     parameter l, w;
     .tox = 10n; .vth0=1.0; //etc.
  endparamset

  paramset nch5v bsim6; // 5volt nmos
     parameter l, w;
     .tox = 20n; .vth0=2.0; //etc.
  endparamset

and maybe I have several paramsets with each name, for binning.
Now, my instance line looks like this:

  nch #(.l(.1u), .w(10u)) M1(d,g,s,b)

and I am not able to override tox on the instance line, because
it is not a parameter for the paramset nch.

-Geoffrey
Received on Thu Jun 17 13:51:55 2004