Forward Message From Geoffrey.Coram - Parameterization for AMS

I am forwarding a message for Geoffrey, Chair of the Verilog-AMS Compact
Modeling.

-----Original Message-----

Steven Sharp wrote:
>
> Without knowing more about what these models look like, it is hard to
> provide feedback about how generates or ordinary parameterization
> could be used. However, generates allow instantiating completely
> different modules based on parameter values, so they are certainly
> powerful enough.

As Shalom notes, the paramsets proposal
http://www.eda.org/verilog-ams/htmlpages/public-docs/paramsets-v4.pdf
discusses many features.

The most basic feature is replacement of Spice model cards, which
can be done with a generate. Suppose I have a netlist which has

 m1 d g s b nmos l=0.5u w=10u

Now, "nmos" is a name that refers to a whole collection of model cards;
some netlist formats call them nmos.0, nmos.1, nmos.2, etc., but some
just call them all "nmos" Each one looks like

..model nmos (level=49 lmin=0.5u lmax=1u wmin=1u wmax=2u
+ vth0=0.7 tox=1e-9 lint=0.1u cjo=1e-15 ...)

where there could be order of 100 parameters, and the simulator picks
the one for which the instance's "w" is in [wmin,wmax] and the "l" is in
[lmin,lmax].

One could do this with a generate statement:

module nmos(d,g,s,b);
  parameter l,w;
  generate
    if (l >= lmin0 && l < lmax0 && w >= wmin0 && w < wmax0)
      M1 #(.level(49) .vth0(0.7) ...) bsim3(.*)
    else if (l > lmin1 ...)
      M1 #(.level(49) .vth0(0.65) ...) bsim3(.*)
    ...
    else
      $strobe("no matching model card");
  endgenerate
endmodule

As Steven noted, you can instantiate different modules
(eg, one of the M1 instantiations could be bsim4 instead).

However, each of the instantiation lines needs to have the
O(100) parameters specified, which looks pretty ugly. All
of the nmos models have to be specified in this master
module: all the bins, fast/slow/nominal corners, pre- and post-layout
models, etc. Typically, corner models are
grouped together: fast nmos with fast pmos, slow nmos with
slow pmos. It's an extra hurdle for the foundry
characterization group to change the way they think.

Also, if I have a transistor MN23 in my design and I want its
transconductance GM, I have to know to ask for MN23.M1.GM
(This is also a problem with overloaded modules.)

-Geoffrey
Received on Sun Jun 27 01:01:32 2004